參數(shù)資料
型號: EFM32G222F128
廠商: Energy Micro
文件頁數(shù): 73/136頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 128KB FLASH 48LQFP
特色產(chǎn)品: EFM32 Gecko
標(biāo)準(zhǔn)包裝: 1
系列: Gecko
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 32MHz
連通性: I²C,IrDA,智能卡,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 37
程序存儲器容量: 128KB(128K x 8)
程序存儲器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.8 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x12b,D/A 1x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TQFP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 914-1027-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
41
www.energymicro.com
Figure 3.2. LSR #3
31
1 0
Carry
Flag
...
0
2
3
4
5
3.3.4.3 LSL
Logical shift left by n bits moves the right-hand 32-n bits of the register Rm, to the left by n places, into
the left-hand 32-n bits of the result. And it sets the right#hand n bits of the result to 0. See Figure 3.3 (p.
You can use he LSL #n operation to multiply the value in the register Rm by 2
n, if the value is regarded
as an unsigned integer or a two’s complement signed integer. Overflow can occur without warning.
When the instruction is LSLS or when LSL #n, with non-zero n, is used in Operand2 with the instructions
MOVS
, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted
out, bit[32-n], of the register Rm. These instructions do not affect the carry flag when used with LSL #0.
Note
If n is 32 or more, then all the bits in the result are cleared to 0.
If n is 33 or more and the carry flag is updated, it is updated to 0.
Figure 3.3. LSL #3
31
1 0
Carry
Flag
...
0
2
3
4
5
3.3.4.4 ROR
Rotate right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the
right-hand 32-n bits of the result. And it moves the right#hand n bits of the register into the left#hand
n
bits of the result. See Figure 3.4 (p. 42) .
When the instruction is RORS or when ROR #n is used in Operand2 with the instructions MOVS, MVNS,
ANDS
, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit rotation, bit[n-1],
of the register Rm.
Note
If n is 32, then the value of the result is same as the value in Rm, and if the carry flag is
updated, it is updated to bit[31] of Rm.
ROR with shift length, n, more than 32 is the same as ROR with shift length n-32.
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