參數(shù)資料
型號: EDS6416AJTA-75-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 4M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝: ROHS COMPLIANT, PLASTIC, TSOP2-54
文件頁數(shù): 10/49頁
文件大?。?/td> 622K
代理商: EDS6416AJTA-75-E
EOL
Product
EDS6416AJTA
Data Sheet E0884E30 (Ver.3.0)
18
Command Truth Table for CKE
CKE
Current State
n – 1 n
/CS
/RAS /CAS /WE Address
Operation
Notes
Self refresh
H
×
INVALID, CLK (n – 1) would exit self refresh
L
H
×
Self refresh recovery
L
H
L
H
×
Self refresh recovery
L
H
L
H
L
×
ILLEGAL
L
H
L
×
ILLEGAL
L
×
Continue self refresh
Self refresh recovery
H
×
Idle after tRC
H
L
H
×
Idle after tRC
H
L
H
L
×
ILLEGAL
H
L
×
ILLEGAL
H
L
H
×
ILLEGAL
H
L
H
×
ILLEGAL
H
L
H
L
×
ILLEGAL
H
L
×
ILLEGAL
Power down
H
×
INVALID, CLK (n – 1) would exit power down
L
H
×
EXIT power down
L
H
L
H
×
EXIT power down
L
×
Continue power down mode
All banks idle
H
×
Refer to operations in Function Truth Table
H
L
H
×
Refer to operations in Function Truth Table
H
L
H
×
Refer to operations in Function Truth Table
H
L
H
×
CBR (auto) Refresh
H
L
OPCODE Refer to operations in Function Truth Table
H
L
H
×
Begin power down next cycle
H
L
H
×
Refer to operations in Function Truth Table
H
L
H
×
Refer to operations in Function Truth Table
H
L
H
×
Self refresh
1
H
L
OPCODE Refer to operations in Function Truth Table
L
H
×
Exit power down next cycle
L
×
Power down
1
Row active
H
×
Refer to operations in Function Truth Table
L
×
Clock suspend
1
Any state other than
H
×
Refer to operations in Function Truth Table
listed above
H
L
×
Begin clock suspend next cycle
2
L
H
×
Exit clock suspend next cycle
L
×
Maintain clock suspend
Remark: H: VIH. L: VIL.
×: VIH or VIL
Notes: 1. Self refresh can be entered only from the all banks idle state. Power down can be entered only from all
banks idle. Clock suspend can be entered only from following states, row active, read, read with auto-
precharge, write and write with auto precharge.
2. Must be legal command as defined in Function Truth Table.
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