參數(shù)資料
型號: EDS2532CABH
廠商: Elpida Memory, Inc.
英文描述: 256M bits SDRAM (8M words x 32 bits)
中文描述: 256M位的SDRAM(800萬字× 32位)
文件頁數(shù): 7/48頁
文件大?。?/td> 578K
代理商: EDS2532CABH
EDS2532CABH
Data Sheet E0395E40 (Ver. 4.0)
7
AC Characteristics (TA = 0 to +70
°
C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
-75
-1A
Parameter
Symbol
min.
max.
min.
max.
Unit
Notes
System clock cycle time
(CL = 2)
tCK
10
10
ns
1
(CL = 3)
tCK
7.5
10
ns
1
CLK high pulse width
tCH
2.5
3
ns
1
CLK low pulse width
tCL
2.5
3
ns
1
Access time from CLK
tAC
5.4
6
ns
1, 2
Data-out hold time
tOH
2.0
2.0
ns
1, 2
CLK to Data-out low impedance
tLZ
0
0
ns
1, 2, 3
CLK to Data-out high impedance tHZ
5.4
6
ns
1, 4
Input setup time
tSI
1.5
2
ns
1
Input hold time
tHI
0.8
1
ns
1
Ref/Active to Ref/Active
command period
Active to Precharge command
period
Active command to column
command (same bank)
Precharge to active command
period
Write recovery or data-in to
precharge lead time
tRC
67.5
70
ns
1
tRAS
45
120000
50
120000
ns
1
tRCD
20
20
ns
1
tRP
20
20
ns
1
tDPL
15
20
ns
1
Last data into active latency
tDAL
2CLK + 20ns —
2CLK + 20ns —
Active (a) to Active (b) command
period
Transition time (rise and fall)
tRRD
15
20
ns
1
tT
0.5
5.0
0.5
5
ns
Refresh period
(4096 refresh cycles)
Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.2V.
2. Access time is measured at 1.2V. Load condition is CL = 30pF.
3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.
tREF
64
64
ms
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