參數(shù)資料
型號(hào): EDS2516CDTA
廠商: Elpida Memory, Inc.
英文描述: 256M bits SDRAM (16M words x 16 bits)
中文描述: 256M位的SDRAM(1,600字× 16位)
文件頁(yè)數(shù): 39/50頁(yè)
文件大小: 703K
代理商: EDS2516CDTA
EDS2516CDTA
DQM Control
The UDQM and LDQM mask the upper and lower bytes of the DQ data, respectively. The timing of UDQM and
LDQM is different during reading and writing.
Prelimimary Data Sheet E0545E40 (Ver. 4.0)
39
Reading
When data is read, the output buffer can be controlled by UDQM and LDQM. By setting UDQM and LDQM to Low,
the output buffer becomes Low-Z, enabling data output. By setting UDQM and LDQM to High, the output buffer
becomes High-Z, and the corresponding data is not output. However, internal reading operations continue. The
latency of UDQM and LDQM during reading is 2 clocks.
Writing
Input data can be masked by UDQM and LDQM. By setting DQM to Low, data can be written. In addition, when
UDQM and LDQM are set to High, the corresponding data is not written, and the previous data is held. The latency
of UDQM and LDQM during writing is 0 clock.
CLK
DQ
out 0
out 1
l
DOD = 2 Latency
out 3
UDQM
LDQM
High-Z
Reading
CLK
DQ
in 0
in 1
l
DID = 0 Latency
in 3
UDQM
LDQM
Writing
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