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參數(shù)資料
| 型號： | EDS2516APTA-75TI |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 256M bits SDRAM WTR (Wide Temperature Range) |
| 中文描述： | 16M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 13/52頁 |
| 文件大小： | 720K |
| 代理商： | EDS2516APTA-75TI |
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EDS2516APTA-TI-E
Data Sheet E0677E10 (Ver. 1.0)
13
Pin Function
CLK (input pin)
CLK is the master clock input to this pin. The other input signals are referred at CLK rising edge.
/CS (input pin)
When /CS is Low, the command input cycle becomes valid. When /CS is High, all inputs are ignored. However,
internal operations (bank active, burst operations, etc.) are held.
/RAS, /CAS, and /WE (input pins)
Although these pin names are the same as those of conventional DRAMs, they function in a different way. These
pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details,
refer to the command operation section.
A0 toA12 (input pins)
Row address (AX0 to AX12) is determined by A0 to A12 at the bank active command cycle CLK rising edge.
Column address is determined by A0 to A8 (see Address Pins Table) at the read or write command cycle CLK rising
edge. And this column address becomes burst access start address.
[Address Pins Table]
Address (A0 to A12)
Part number
Row address
Column address
EDS2516APTA
AX0 to AX12
AY0 to AY8
A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are precharged.
But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0 and BA1 (BS) is
precharged. For details refer to the command operation section.
BA0 and BA1 (input pin)
BA0 and BA1
are bank select signal (BS). (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0
BA1
Bank 0
L
L
Bank 1
H
L
Bank 2
L
H
Bank 3
Remark: H: VIH. L: VIL.
×
: VIH or VIL
CKE (input pin)
This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising edge is valid. If CKE is
Low, the next CLK rising edge is invalid. This pin is used for power-down mode, clock suspend mode and self
refresh mode.
H
H
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| EDS2516CDTA-75-E | 256M bits SDRAM (16M words x 16 bits) |
| EDS2516APTA-75 | 256M bits SDRAM |
| EDS2516APTA-75L | 256M bits SDRAM |
| EDS2516APTA-7A | 256M bits SDRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDS2516APTA-75TI-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits SDRAM WTR (Wide Temperature Range) |
| EDS2516APTA-7A | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits SDRAM |
| EDS2516APTA-7A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits SDRAM |
| EDS2516APTA-7AL | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits SDRAM |
| EDS2516APTA-7AL-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits SDRAM |
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