參數(shù)資料
型號: EDS2516APSA
廠商: Elpida Memory, Inc.
英文描述: 256M bits SDRAM
中文描述: 256M比特內(nèi)存
文件頁數(shù): 7/50頁
文件大?。?/td> 703K
代理商: EDS2516APSA
EDS2516CDTA
AC Characteristics (TA = 0 to +70
°
C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
Prelimimary Data Sheet E0545E40 (Ver. 4.0)
7
-75
Parameter
System clock cycle time
(CL = 2)
Symbol
min.
max.
Unit
Notes
tCK
10
ns
1
(CL = 3)
tCK
7.5
ns
1
CLK high pulse width
tCH
2.5
ns
1
CLK low pulse width
tCL
2.5
ns
1
Access time from CLK
tAC
6
ns
1, 2
Data-out hold time
tOH
3
ns
1, 2
CLK to Data-out low impedance
tLZ
0
ns
1, 2, 3
CLK to Data-out high impedance
tHZ
6
ns
1, 4
Input setup time
tSI
1.5
ns
1
Input hold time
tHI
0.8
ns
1
Ref/Active to Ref/Active command period
tRC
67.5
ns
1
Active to Precharge command period
tRAS
45
120000
ns
1
Active command to column command (same bank)
tRCD
20
ns
1
Precharge to active command period
tRP
20
ns
1
Write recovery or data-in to precharge lead time
tDPL
15
ns
1
Last data into active latency
tDAL
2CLK + 20ns
Active (a) to Active (b) command period
tRRD
15
ns
1
Transition time (rise and fall)
tT
0.5
5
ns
Refresh period
(8192 refresh cycles)
Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.2V.
2. Access time is measured at 1.2V. Load condition is CL = 30pF.
3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.
tREF
64
ms
相關PDF資料
PDF描述
EDS2516APSA-75 256M bits SDRAM
EDS2516APSA-75L 256M bits SDRAM
EDS2516APSA-7A 256M bits SDRAM
EDS2516APSA-7AL 256M bits SDRAM
EDS2516APTA 256M bits SDRAM
相關代理商/技術(shù)參數(shù)
參數(shù)描述
EDS2516APSA-75 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits SDRAM
EDS2516APSA-75L 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits SDRAM
EDS2516APSA-7A 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits SDRAM
EDS2516APSA-7AL 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits SDRAM
EDS2516APTA 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits SDRAM