參數(shù)資料
型號(hào)： EDS2516APSA-7A
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 256M bits SDRAM
中文描述： 16M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA60
封裝： MICRO, BGA-60
文件頁數(shù)： 11/50頁
文件大小： 703K
代理商： EDS2516APSA-7A
EDS2516CDTA
Prelimimary Data Sheet E0545E40 (Ver. 4.0)
11
Pin Function
CLK (input pin)
CLK is the master clock input. Other inputs signals are referenced to the CLK rising edge.
CKE (input pins)
CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge is valid; otherwise it is
invalid. If the CLK rising edge is invalid, the internal clock is not issued and the Synchronous DRAM suspends
operation.
When the Synchronous DRAM is not in burst mode and CKE is negated, the device enters power down mode.
During power down mode, CKE must remain low.
/CS (input pins)
/CS low starts the command input cycle. When /CS is high, commands are ignored but operations continue.
/RAS, /CAS, and /WE (input pins)
/RAS, /CAS and /WE have the same symbols on conventional DRAM but different functions. For details, refer to the
command table.
A0 to A12 (input pins)
Row address (AX0 to AX12) is determined by A0 to A12 at the bank active command cycle CLK rising edge.
Column address is determined by A0 to A8 (see Address Pins Table) at the read or write command cycle CLK rising
edge. And this column address becomes burst access start address.
[Address Pins Table]
Address (A0 to A12)
Part number
Row address
Column address
EDS2516CD
AX0 to AX12
AY0 to AY8
A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are precharged.
But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0 and BA1 (BS) is
precharged. For details refer to the command operation section.
BA0 and BA1 (input pin)
BA0 and BA1 are bank select signal. (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0
BA1
Bank 0
L
L
Bank 1
H
L
Bank 2
L
H
Bank 3
H
H
Remark: H: VIH. L: VIL.
相關(guān)PDF資料
PDF描述
EDS2516APSA-7AL 256M bits SDRAM
EDS2516APTA 256M bits SDRAM
EDS2516CDTA 256M bits SDRAM (16M words x 16 bits)
EDS2532AABJ-6B 256M bits SDRAM (8M words ?32 bits)
EDS2532AABJ-6B-E 256M bits SDRAM (8M words ?32 bits)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EDS2516APSA-7AL 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits SDRAM
EDS2516APTA 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits SDRAM
EDS2516APTA-60 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits SDRAM
EDS2516APTA-60-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits SDRAM
EDS2516APTA-60L 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits SDRAM
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