參數資料
型號: EDS1232CATA-75L
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 128M bits SDRAM
中文描述: 4M X 32 SYNCHRONOUS DRAM, 5.4 ns, PDSO86
封裝: PLASTIC, TSOP2-86
文件頁數: 39/55頁
文件大小: 564K
代理商: EDS1232CATA-75L
EDS1232CABB, EDS1232CATA
Preliminary Data Sheet E0247E40 (Ver. 4.0)
39
Read command to Precharge command interval (same bank)
When the precharge command is executed for the same bank as the read command that preceded it, the minimum
interval between the two commands is one clock. However, since the output buffer then becomes High-Z after the
clocks defined by lHZP, there is a case of interruption to burst read data output will be interrupted, if the precharge
command is input during burst read. To read all data by burst read, the clocks defined by lEP must be assured as
an interval from the final data output to precharge command execution.
CLK
Command
DQ
READ
PRE/PALL
out A0
out A1
out A2
out A3
CL=2
lEP = -1 cycle
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 2, BL = 4)
CLK
Command
DQ
READ
PRE/PALL
out A0
out A1
out A2
out A3
CL=3
lEP = -2 cycle
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 3, BL = 4)
CLK
Command
DQ
READ
PRE/PALL
out A0
High-Z
lHZP = 2
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 2, BL = 1, 2, 4, 8)
CLK
Command
DQ
READ
PRE/PALL
out A0
lHZP =3
High-Z
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 3, BL = 1, 2, 4, 8)
相關PDF資料
PDF描述
EDS1232CABB-1A-E 128M bits SDRAM
EDS1232CABB-75-E 128M bits SDRAM
EDS1232CATA 128M bits SDRAM
EDS2516AFTA 256M bits SDRAM
EDS2516AFTA-6B-E 256M bits SDRAM
相關代理商/技術參數
參數描述
EDS1232ECBH-75 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits SDRAM
EDS1232ECBH-75-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits SDRAM
EDS1232ECBH-9A 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits SDRAM
EDS1232ECBH-9A-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits SDRAM
EDS1232ECBH-9ATT 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits SDRAM 128M bits SDRAM