參數(shù)資料
型號: EDS1232CABB-75-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 128M bits SDRAM
中文描述: 4M X 32 SYNCHRONOUS DRAM, 5.4 ns, PBGA90
封裝: FBGA-90
文件頁數(shù): 14/55頁
文件大?。?/td> 564K
代理商: EDS1232CABB-75-E
EDS1232CABB, EDS1232CATA
Preliminary Data Sheet E0247E40 (Ver. 4.0)
14
Read command (/CS, /CAS = Low, /RAS, /WE = High)
Read data is available after /CAS latency requirements have been met. This command sets the burst start address
given by the column address.
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
(Bank select)
Col.
Column Address and and Read Command
CBR (auto) refresh command (/CS, /RAS, /CAS = Low, /WE, CKE = High)
This command is a request to begin the CBR (auto)
refresh operation. The refresh address is generated internally.
Before executing CBR (auto) refresh, all banks must be precharged. After this cycle, all banks will be in the idle
(precharged) state and ready for a row activate command. During tRC period (from refresh command to refresh or
activate command), the Synchronous DRAM cannot accept any other command
Add
A10
(Bank select)
/WE
/CAS
/RAS
/CS
CKE
CLK
H
CBR (auto) Refresh Command
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