參數(shù)資料
型號(hào): EDS1232AATA-60L-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 128M bits SDRAM (4M words x 32 bits)
中文描述: 4M X 32 SYNCHRONOUS DRAM, 5.4 ns, PDSO86
封裝: ROHS COMPLIANT, PLASTIC, TSOP2-86
文件頁數(shù): 40/55頁
文件大?。?/td> 564K
代理商: EDS1232AATA-60L-E
EDS1232CABB, EDS1232CATA
Preliminary Data Sheet E0247E40 (Ver. 4.0)
40
Write command to Precharge command interval (same bank)
When the precharge command is executed for the same bank as the write command that preceded it, the minimum
interval between the two commands is 1 clock. However, if the burst write operation is unfinished, the input data
must be masked by means of DQM for assurance of the clock defined by tDPL.
CLK
Command
DQ
WRIT
PRE/PALL
tDPL
DQM
CLK
in A0
in A1
Command
DQ
WRIT
PRE/PALL
DQM
tDPL
WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To stop write operation))
CLK
in A0
in A1
in A2
Command
DQ
WRIT
PRE/PALL
in A3
DQM
tDPL
WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To write all data))
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