參數(shù)資料
型號： EDS1232AASE-60L-E
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： Circular Connector; No. of Contacts:6; Series:; Body Material:Aluminum Alloy; Connecting Termination:Solder; Connector Shell Size:20; Circular Contact Gender:Socket; Circular Shell Style:Cable Receptacle; Insert Arrangement:20-17 RoHS Compliant: No
中文描述： 4M X 32 SYNCHRONOUS DRAM, 5.4 ns, PBGA90
封裝： ROHS COMPLIANT, FBGA-90
文件頁數(shù)： 6/55頁
文件大?。?/td> 564K
代理商： EDS1232AASE-60L-E
EDS1232CABB, EDS1232CATA
Preliminary Data Sheet E0247E40 (Ver. 4.0)
6
DC Characteristics (TA = 0 to +70
°
C, VDD, VDDQ = 2.5V
±
0.2V, VSS, VSSQ = 0V)
Parameter
/CAS latency
Symbol
Grade
max.
Unit
Test condition
Notes
Operating current
(CL = 2)
IDD1
-75
-1A
-75
-1A
105
100
105
100
1
mA
1
(CL = 3)
IDD1
mA
Burst length = 1
tRC
≥
tRC (min.)
IO = 0mA
One bank active
Standby current in power down
Standby current in power down
(input signal stable)
IDD2P
mA
IDD2PS
1
mA
CKE
≤
VIL (max.) tCK = 15ns
CKE
≤
VIL (max.) tCK =
∞
Standby current in non power
down
IDD2N
20
mA
CKE
≥
VIH (min.) tCK = 15ns
CS
≥
VIH (min.)
Input signals are changed one
time during 30ns
Standby current in non power
down
(input signal stable)
Active standby current in power
down
Active standby current in power
down (input signal stable)
IDD2NS
8
mA
CKE
≥
VIH (min.) tCK =
∞
IDD3P
5
mA
CKE
≤
VIL (max.) tCK = 15ns
IDD3PS
4
mA
CKE
≤
VIL (max.), tCK =
∞
Active standby current in non
power down
IDD3N
25
mA
CKE
≥
VIH (min.), tCK = 15 ns,
/CS
≥
VIH (min.),
Input signals are changed one
time during 30ns.
Active standby current in non
power down
(input signal stable)
IDD3NS
15
mA
CKE
≥
VIH (min.), tCK =
∞
,
Burst operating current
IDD4
-75
-1A
-75
-1A
150
130
210
200
mA
tCK
≥
tCK (min.),
IO = 0mA, All banks active
2
Refresh current
IDD5
mA
tRC
≥
tRC (min.)
3
Self refresh current
IDD6
2.0
mA
VIH
≥
VDD
0.2V,
VIL
≤
GND + 0.2V
Self refresh current
(L-version)
Notes: 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, IDD1 is measured condition that addresses are changed only one time during tCK (min.).
2. IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open.
In addition to this, IDD4 is measured condition that addresses are changed only one time during tCK
(min.).
3. IDD5 is measured on condition that addresses are changed only one time during tCK (min.).
IDD6
-xxL
0.6
mA
DC Characteristics 2 (TA = 0 to +70
°
C, VDD, VDDQ = 2.5V
±
0.2V, VSS, VSSQ = 0V)
Parameter
Symbol
min.
max.
Unit
Test condition
Notes
Input leakage current
ILI
–1.0
1.0
μA
0 = VIN = VDDQ, VDDQ = VDD,
All other pins not under test = 0V
0 = VIN = VDDQ DOUT is disabled
Output leakage current
Output high voltage
Output low voltage
ILO
–1.5
1.5
μA
VOH
2.0
—
V
IOH = –1mA
VOL
—
0.4
V
IOL = 1mA
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