參數(shù)資料
型號(hào): EDS1232AABB-75L
英文描述: SDRAM|4X1MX32|CMOS|BGA|90PIN|PLASTIC
中文描述: 內(nèi)存| 4X1MX32 |的CMOS | BGA封裝| 90PIN |塑料
文件頁數(shù): 7/55頁
文件大?。?/td> 570K
代理商: EDS1232AABB-75L
EDS1232AABB, EDS1232AATA
Data Sheet E0205E30 (Ver. 3.0)
15
Self refresh entry command (/CS, /RAS, /CAS, CKE = Low, /WE = High)
After the command execution, self refresh operation continues while CKE remains low. When CKE goes high, the
Synchronous DRAM exits the self refresh mode. During self refresh mode, refresh interval and refresh operation are
performed internally, so there is no need for external control. Before executing self refresh, all banks must be
precharged.
/WE
/CAS
/RAS
/CS
CKE
CLK
Add
A10
BA0, BA1
(Bank select)
Self Refresh Entry Command
Burst stop command (/CS = /WE = Low, /RAS, /CAS = High)
This command can stop the current burst operation.
/WE
/CAS
/RAS
/CS
CKE
CLK
Add
A10
BA0, BA1
(Bank select)
H
Burst Stop Command in Full Page Mode
No operation (/CS = Low, /RAS, /CAS, /WE = High)
This command is not an execution command. No operations begin or terminate by this command.
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
(Bank select)
No Operation
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