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參數(shù)資料
| 型號： | EDS1232AABB-75L |
| 英文描述： | SDRAM|4X1MX32|CMOS|BGA|90PIN|PLASTIC |
| 中文描述： | 內(nèi)存| 4X1MX32 |的CMOS | BGA封裝| 90PIN |塑料 |
| 文件頁數(shù)： | 4/55頁 |
| 文件大?。?/td> | 570K |
| 代理商： | EDS1232AABB-75L |
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EDS1232AABB, EDS1232AATA
Data Sheet E0205E30 (Ver. 3.0)
12
Command Operation
Mode register set command (/CS, /RAS, /CAS, /WE)
The Synchronous DRAM has a mode register that defines how the device operates. In this command, A0 through
A11 are the data input pins. After power on, the mode register set command must be executed to initialize the
device. The mode register can be set only when all banks are in idle state. During 2CLK (tRSC) following this
command, the Synchronous DRAM cannot accept any other commands.
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
(Bank select)
Mode Register Set Command
Activate command (/CS, /RAS = Low, /CAS, /WE = High)
The Synchronous DRAM has four banks, each with 8,192 rows. This command activates the bank selected by BA0
and BA1 and a row address selected by A0 through A11. This command corresponds to a conventional DRAM's
/RAS falling.
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0, BA1
Row
(Bank select)
Row Address Strobe and Bank Activate Command
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| EDS1232AABB-75L-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits SDRAM |
| EDS1232AASE | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits SDRAM (4M words x 32 bits) |
| EDS1232AASE-60-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits SDRAM (4M words x 32 bits) |
| EDS1232AASE-60L-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits SDRAM (4M words x 32 bits) |
| EDS1232AASE-75-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits SDRAM (4M words x 32 bits) |
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