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參數(shù)資料
| 型號： | EDE5108AGSE-6C-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | LJT 13C 13#22M PIN RECP |
| 中文描述： | 64M X 8 DDR DRAM, 0.45 ns, PBGA60 |
| 封裝： | ROHS COMPLIANT, FBGA-60 |
| 文件頁數(shù)： | 45/66頁 |
| 文件大?。?/td> | 697K |
| 代理商： | EDE5108AGSE-6C-E |
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EDE5104ABSE, EDE5108ABSE, EDE5116ABSE
Data Sheet E0323E90 (Ver. 9.0)
45
WRIT
NOP
WRIT
CK
/CK
T0
T2
T4
T6
T8
T10
T1
T3
T5
T7
T9
T11
Command
DQS, /DQS
DQ
NOP
WL = 3
Burst interrupt is only
allowed at this timing.
Write Interrupt by Write (WL = 3, BL = 8)
in
A0
in
A1
in
A2
in
A3
in
B0
in
B1
in
B2
in
B3
in
B4
in
B5
in
B6
in
B7
A
B
Notes :1. Write burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.
2. Write burst of 8 can only be interrupted by another write command. Write burst interruption by read
command or precharge command is prohibited.
3. Write burst interrupt must occur exactly two clocks after previous write command. Any other write burst
interrupt timings are prohibited.
4. Write burst interruption is allowed to any bank inside DRAM.
5. Write burst with auto precharge enabled is not allowed to interrupt.
6. Write burst interruption is allowed by another write with auto precharge command.
7. All command timings are referenced to burst length set in the mode register. They are not referenced to
actual burst. For example, minimum write to precharge timing is WL+BL/2+tWR where tWR starts with
the rising clock after the un-interrupted burst end and not from the end of actual burst end.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDE5104AGSE-6E-E | Circular Connector; No. of Contacts:13; Series:MS27468; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:11; Circular Contact Gender:Socket; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:11-13 RoHS Compliant: No |
| EDE5108AGSE-6E-E | Circular Connector; No. of Contacts:2; Series:MS27468; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:11; Circular Contact Gender:Socket; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:11-2 RoHS Compliant: No |
| EDE5104ABSE-4A-E | 512M bits DDR2 SDRAM |
| EDE5108ABSE-4A-E | 512M bits DDR2 SDRAM |
| EDE5104ABSE-5C-E | 512M bits DDR2 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDE5108AGSE-6E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5108AHBG | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5108AHBG-4A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5108AHBG-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5108AHBG-6E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
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