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參數(shù)資料
| 型號(hào)： | EDE5104ABSE-5C-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M bits DDR2 SDRAM |
| 中文描述： | 128M X 4 DDR DRAM, 0.5 ns, PBGA64 |
| 封裝： | ROHS COMPLIANT, FBGA-64 |
| 文件頁(yè)數(shù)： | 1/66頁(yè) |
| 文件大小： | 697K |
| 代理商： | EDE5104ABSE-5C-E |
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Document No. E0323E90 (Ver. 9.0)
Date Published September 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2002-2005
DATA SHEET
512M bits DDR2 SDRAM
EDE5104ABSE (128M words
×
4 bits)
EDE5108ABSE (64M words
×
8 bits)
EDE5116ABSE (32M words
×
16 bits)
Description
The EDE5104ABSE is a 512M bits DDR2 SDRAM
organized as 33,554,432 words
×
4 bits
×
4 banks.
The EDE5108ABSE is a 512M bits DDR2 SDRAM
organized as 16,777,216 words
×
8 bits
×
4 banks.
They are packaged in 64-ball FBGA (
μ
BGA
) package.
The EDE5116ABSE is a 512M bits DDR2 SDRAM
organized as 8,388,608 words
×
16 bits
×
4 banks.
It is packaged in 84-ball FBGA (
μ
BGA) package.
Features
Power supply: VDD, VDDQ
=
1.8V
±
0.1V
Double-data-rate architecture: two data transfers per
clock cycle
Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
Four internal banks for concurrent operation
Data mask (DM) for write data
Burst lengths: 4, 8
/CAS Latency (CL): 3, 4, 5
Auto precharge operation for each burst access
Auto refresh and self refresh modes
7.8
μ
s average periodic refresh interval
SSTL_18 compatible I/O
Posted CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
Programmable RDQS, /RDQS output for making
×
8
organization compatible to
×
4 organization
/DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation.
FBGA (
μ
BGA) package with lead free solder
(Sn-Ag-Cu)
RoHS compliant
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDE5108ABSE-5C-E | 512M bits DDR2 SDRAM |
| EDE5108AESK-4A-E | 512M bits DDR2 SDRAM |
| EDE5108AESK-5C-E | 512M bits DDR2 SDRAM |
| EDE5108AESK-6E-E | 512M bits DDR2 SDRAM |
| EDE5108GBSA-4A-E | 512M bits DDR-II SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDE5104AESK | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5104AESK-4A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5104AESK-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5104AESK-6E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5104AGSE | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
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