參數(shù)資料
型號： EDE5108ABSE
廠商： Elpida Memory, Inc.
英文描述： 512M bits DDR2 SDRAM
中文描述： 512M比特DDR2 SDRAM內(nèi)存
文件頁數(shù)： 49/66頁
文件大?。?/td> 697K
代理商： EDE5108ABSE
EDE5104ABSE, EDE5108ABSE, EDE5116ABSE
Data Sheet E0323E90 (Ver. 9.0)
49
Burst Write followed by Precharge
Minimum Write to Precharge Command spacing to the same bank = WL + BL/2 clocks + tWR
For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the precharge
command can be issued. This delay is known as a write recovery time (tWR) referenced from the completion of the
burst write to the precharge command. No precharge command should be issued prior to the tWR delay, as DDR2
SDRAM allows the burst interrupt operation only Read by Read or Write by Write at the boundary of burst 4.
in3
in1
NOP
CK
/CK
T0
T1
T2
T3
T4
T5
T6
T7
T8
Command
DQS, /DQS
DQ
>
tWR
=
Completion of
the Burst Write
WL = 3
in0
in2
Posted
WRIT
PRE
Burst Write Followed by Precharge (WL = (RL-1) =3)
Posted
WRIT
CK
/CK
T0
T1
T2
T3
T4
T5
T6
T7
T9
Command
DQS, /DQS
DQ
WL = 4
in0
in1
in2
in3
PRE
>
tWR
=
Completion of
the Burst Write
NOP
Burst Write Followed by Precharge (WL = (RL-1) = 4)
Posted
WRIT
NOP
CK
/CK
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T11
Command
DQS, /DQS
DQ
WL = 4
in0
in1
in2
in3
in4
in5
in6
in7
>
tWR
=
Completion of
the Burst Write
PRE
Burst Write Followed by Precharge (WL = (RL-1) = 4,BL= 8)
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