參數(shù)資料
型號(hào)： EDE5104GBSA-4A-E
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 512M bits DDR-II SDRAM
中文描述： 128M X 4 DDR DRAM, 0.6 ns, PBGA64
封裝： MICRO, BGA-64
文件頁(yè)數(shù)： 31/66頁(yè)
文件大?。?/td> 697K
代理商： EDE5104GBSA-4A-E
EDE5104ABSE, EDE5108ABSE, EDE5116ABSE
Data Sheet E0323E90 (Ver. 9.0)
31
Extended Mode Register Set for OCD Impedance Adjustment
OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs are driven out
by DDR2 SDRAM and drive of RDQS is dependent on EMRS bit enabling RDQS operation. In Drive(1) mode, all
DQ, DQS (and RDQS) signals are driven high and all /DQS signals are driven low. In drive(0) mode, all DQ, DQS
(and RDQS) signals are driven low and all /DQS signals are driven high.
In adjust mode, BL = 4 of operation code data must be used. In case of OCD calibration default, output driver
characteristics follow approximate nominal V/I curve for 18
output drivers, but are not guaranteed. If tighter control
is required, which is controlled within 18
±
3
driver impedance range, OCD must be used.
[OCD Mode Set Program]
A9
A8
A7
Operation
0
0
0
OCD calibration mode exit
0
0
1
Drive (1) DQ, DQS, (RDQS) high and /DQS low
0
1
0
Drive (0) DQ, DQS, (RDQS) low and /DQS high
1
0
0
Adjust mode
1
1
1
OCD calibration default
OCD Impedance Adjustment
To adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a 4bit burst code
to DDR2 SDRAM as in OCD Adjustment Program table. For this operation, burst length has to be set to BL = 4 via
MRS command before activating OCD and controllers must drive this burst code to all DQs at the same time. DT0 in
OCD Adjustment Program table means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output
impedance is adjusted for all DDR2 SDRAM DQs simultaneously and after OCD calibration, all DQs of a given
DDR2 SDRAM will be adjusted to the same driver strength setting. The maximum step count for adjustment is 16
and when the limit is reached, further increment or decrement code has no effect. The default setting may be any
step within the 16-step range.
[OCD Adjustment Program]
4bits burst data inputs to all DQs
Operation
DT0
DT1
DT2
DT3
Pull-up driver strength
Pull-down driver strength
0
0
0
0
NOP
NOP
0
0
0
1
Increase by 1 step
NOP
0
0
1
0
Decrease by 1 step
NOP
0
1
0
0
NOP
Increase by 1 step
1
0
0
0
NOP
Decrease by 1 step
0
1
0
1
Increase by 1 step
Increase by 1 step
0
1
1
0
Decrease by 1 step
Increase by 1 step
1
0
0
1
Increase by 1 step
Decrease by 1 step
1
0
1
0
Decrease by 1 step
Decrease by 1 step
Other combinations
Reserved
相關(guān)PDF資料
PDF描述
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EDE5108AJBG-6E-E 512M bits DDR2 SDRAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EDE5104GBSA-5A-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR-II SDRAM
EDE5108ABSE 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM
EDE5108ABSE-4A-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM
EDE5108ABSE-5C-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM
EDE5108ABSE-AE 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM for HYPER DIMM
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