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參數(shù)資料
| 型號： | EDE5104AESK |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 512M bits DDR2 SDRAM |
| 中文描述： | 512M比特DDR2 SDRAM內(nèi)存 |
| 文件頁數(shù)： | 56/66頁 |
| 文件大?。?/td> | 697K |
| 代理商： | EDE5104AESK |
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EDE5104ABSE, EDE5108ABSE, EDE5116ABSE
Data Sheet E0323E90 (Ver. 9.0)
56
Power-Down [PDEN]
Power-down is synchronously entered when CKE is registered low (along with NOP or deselect command). CKE is
not allowed to go low while mode register or extended mode register command time, or read or write operation is in
progress. CKE is allowed to go low while any of other operations such as row activation, precharge or auto-
precharge, or auto-refresh is in progress, but power-down IDD spec will not be applied until finishing those
operations. Timing diagrams are shown in the following pages with details for entry into power down.
The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting
power-down mode for proper read operation.
If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down
occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down
deactivates the input and output buffers, excluding CK, /CK, ODT and CKE. Also the DLL is disabled upon entering
precharge power-down or slow exit active power-down, but the DLL is kept enabled during fast exit active power-
down. In power-down mode, CKE low and a stable clock signal must be maintained at the inputs of the DDR2
SDRAM, and ODT should be in a valid state but all other input signals are “Don’t Care”. CKE low must be
maintained until tCKE has been satisfied. Power-down duration is limited by 9 times tREFI of the device.
The power-down state is synchronously exited when CKE is registered high (along with a NOP or deselect
command). CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be
applied with power-down exit latency, tXP, tXARD, or tXARDS, after CKE goes high. Power-down exit latency is
defined at AC Characteristics table of this data sheet.
CK
/CK
CKE
Command
VIH or VIL
tXP, tXARD,
tXARDS
Enter power-down mode
tCKE
tCKE
Exit power-down mode
Power Down
tCKE
tIH
tIS
tIH
tIS
tIH
tIS
tIH
tIH
tIS
VALID
VALID
VALID
NOP
NOP
VALID
Read to Power-Down Entry
CK
Command
CKE
DQ
DQS
/DQS
Command
CKE
DQ
DQS
/DQS
/CK
AL + CL
AL + CL
BL=4
BL=8
T0
Tx
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
T1
T2
Tx+1
Tx+7
Tx+8
Tx+9
READ
out
0
out
1
out
2
out
3
out
0
out
1
out
2
out
3
out
4
out
5
out
6
out
7
VIH
VIH
CKE should be kept high until the end of burst operation.
CKE should be kept high until the end of burst operation.
Read operation starts with a read command and
T0
Tx
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
T1
T2
Tx+1
Tx+7
Tx+8
Tx+9
READ
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDE5104AESK-4A-E | 512M bits DDR2 SDRAM |
| EDE5104AESK-5C-E | 512M bits DDR2 SDRAM |
| EDE5104AESK-6E-E | 512M bits DDR2 SDRAM |
| EDE5104GBSA-4A-E | 512M bits DDR-II SDRAM |
| EDE5104AJSE | EDE5104AJSE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDE5104AESK-4A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5104AESK-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5104AESK-6E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5104AGSE | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5104AGSE_1 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
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