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參數(shù)資料
| 型號： | EDD2508AETA-7B-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 256M bits DDR SDRAM |
| 中文描述： | 32M X 8 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | ROHS COMPLIANT, PLASTIC, TSOP2-66 |
| 文件頁數(shù)： | 42/52頁 |
| 文件大?。?/td> | 492K |
| 代理商： | EDD2508AETA-7B-E |
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EDD2508AETA, EDD2516AETA
Data Sheet E0859E50 (Ver. 5.0)
42
DM Control
DM can mask input data. In
×
16 products, UDM and LDM can mask the upper and lower byte of input data,
respectively. By setting DM to low, data can be written. When DM is set to High, the corresponding data is not
written, and the previous data is held. The latency between DM input and enabling/disabling mask function is 0.
Mask
Mask
DQS
DQ
DM
t1
t2
t3
t4
t5
t6
Write mask latency = 0
DM Control
Self-Refresh
The self-refresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered
down. When in the self-refresh mode, the DDR SDRAM retains data without external clocking. The self-refresh
command is initiated like an auto-refresh command except CKE is disabled (low). The DLL is automatically disabled
upon entering self-refresh, and is automatically enabled upon exiting self-refresh. Any time the DLL is enabled a
DLL reset must follow and 200 clock cycles should occur before a read command can be issued. Input signals
except CKE are “Don’t care” during self-refresh. Since CKE is an SSTL2 input, VREF must be maintained during
self-refresh.
The procedure for exiting self-refresh requires a sequence of commands. First, CK must be stable prior to CKE
going back high. Once CKE is high, the DDR SDRAM must have NOP commands issued for tSNR because time is
required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL
requirements is to apply NOPs for 200 clock cycles before applying any other command.
The use of self-refresh mode introduces the possibility that an internally timed event can be missed when CKE is
raised for exit from self-refresh mode. Upon exit from self-refresh an extra auto-refresh command is recommended.
Notes: 1. Device must be in the “All banks idle” state prior to entering self-refresh mode.
2. tSRD is applied for a read or a read with autoprecharge command.
3. tSNR is applied for any command except a read or a read with autoprecharge command.
Self-Refresh
CK
t0
t2
t1
tm
tn
CKE
Command
t3
t4
t5
t6
/CK
tCK
tCH tCL
tIS
tIS
tIS tIH
Valid
NOP
NOP
SELF
NOP
tRP*
1
≥
tSNR*
3
≥
tSRD*
2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDD2516AETA | 256M bits DDR SDRAM |
| EDD2516AETA-5B-E | 256M bits DDR SDRAM |
| EDD2516AETA-5C-E | 256M bits DDR SDRAM |
| EDD2516AETA-6B-E | 256M bits DDR SDRAM |
| EDD2516AETA-7B-E | 256M bits DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDD2508AJTA | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR SDRAM |
| EDD2508AJTA-6B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR SDRAM |
| EDD2508AJTA-7A | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR SDRAM |
| EDD2508AJTA-7B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR SDRAM |
| EDD2508AKTA | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR SDRAM |
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