參數(shù)資料
型號: EDD2508AETA-7B-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 256M bits DDR SDRAM
中文描述: 32M X 8 DDR DRAM, 0.75 ns, PDSO66
封裝: ROHS COMPLIANT, PLASTIC, TSOP2-66
文件頁數(shù): 12/52頁
文件大?。?/td> 492K
代理商: EDD2508AETA-7B-E
EDD2508AETA, EDD2516AETA
Data Sheet E0859E50 (Ver. 5.0)
12
Timing Parameter Measured in Clock Cycle
Number of clock cycle
tCK
5ns
6ns
7.5ns
Parameter
Symbol
min.
max.
min.
max.
min.
max.
Unit
Write to pre-charge command delay
(same bank)
Read to pre-charge command delay
(same bank)
Write to read command delay
(to input all data)
Burst stop command to write
command delay
(CL = 2)
tWPD
1 + BL/2
+ tWR
1 + BL/2
+ tWR
1 + BL/2
+ tWR
tCK
tRPD
BL/2
BL/2
BL/2
tCK
tWRD
1 + BL/2
+ tWTR
1 + BL/2
+ tWTR
1 + BL/2
+ tWTR
tCK
tBSTW
2
tCK
(CL = 2.5)
tBSTW
3
3
tCK
(CL = 3)
tBSTW
3
3
3
tCK
Burst stop command to DQ High-Z
(CL = 2)
tBSTZ
2
2
tCK
(CL = 2.5)
tBSTZ
2.5
2.5
2.5
2.5
tCK
(CL = 3)
tBSTZ
3
3
3
3
3
3
tCK
Read command to write command
delay (to output all data)
(CL = 2)
tRWD
2 + BL/2
tCK
(CL = 2.5)
tRWD
3 + BL/2
3 + BL/2
tCK
(CL = 3)
tRWD
3 + BL/2
3 + BL/2
3 + BL/2
tCK
Pre-charge command to High-Z
(CL = 2)
tHZP
2
2
tCK
(CL = 2.5)
tHZP
2.5
2.5
2.5
2.5
tCK
(CL = 3)
tHZP
3
3
3
3
3
3
tCK
Write command to data in latency
tWCD
1
1
1
1
1
1
tCK
Write recovery
tWR
3
3
2
tCK
DM to data in latency
tDMD
0
0
0
0
0
0
tCK
Self-refresh exit to non-read
command
tSNR
15
12
10
tCK
Self-refresh exit to read command
tSRD
200
200
200
tCK
Power down entry
tPDEN
1
1
1
1
1
1
tCK
Power down exit to command input
tPDEX
1
1
1
tCK
Active to Precharge command period tRAS
8
7
6
tCK
Active to Active/Auto-refresh
command period
Auto-refresh to Active/Auto-refresh
command period
tRC
11 (-5B)
12 (-5C)
10
9
tCK
tRFC
14
12
10
tCK
Active to Read/Write delay
tRCD
3 (-5B)
4 (-5C)
3 (-5B)
4 (-5C)
3
3
tCK
Precharge to active command period tRP
3
3
tCK
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