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參數(shù)資料
| 型號： | EDD2504AKTA-7B-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 256M bits DDR SDRAM (64M words x 4 bits) |
| 中文描述： | 64M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | ROHS COMPLIANT, PLASTIC, TSOP2-66 |
| 文件頁數(shù)： | 11/49頁 |
| 文件大小： | 441K |
| 代理商： | EDD2504AKTA-7B-E |
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EDD2504AKTA
Data Sheet E0457E10 (Ver. 1.0)
11
Pin Function
CK, /CK (input pins)
The CK and the /CK are the master clock inputs. All inputs except DM, DQS and DQs are referred to the cross point
of the CK rising edge and the /CK falling edge. When a read operation, DQS and DQs are referred to the cross point
of the CK and the /CK. When a write operation, DQS and DQs are referred to the cross point of the DQS and the
VREF level. DQS for write operation is referred to the cross point of the CK and the /CK. CK is the master clock
input to this pin. The other input signals are referred at CK rising edge.
/CS (input pin)
When /CS is Low, commands and data can be input. When /CS is High, all inputs are ignored. However, internal
operations (bank active, burst operations, etc.) are held.
/RAS, /CAS, and /WE (input pins)
These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.
See "Command operation".
A0 toA12 (input pins)
Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the
/CK falling edge in a bank active command cycle. Column address (See “Address Pins Table”) is loaded via the A0
to the A9 and A11 at the cross point of the CK rising edge and the /CK falling edge in a read or a write command
cycle. This column address becomes the starting address of a burst operation.
[Address Pins Table]
Address (A0 to A12)
Part number
Row address
Column address
EDD2504AK
AX0 to AX12
AY0 to AY9, AY11
A10 (AP) (input pin)
A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If
A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low when a precharge
command is issued, only the bank that is selected by BA1/BA0 is precharged. If A10 = High when read or write
command, auto-precharge function is enabled. While A10 = Low, auto-precharge function is disabled.
BA0 and BA1 (input pins)
BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See
Bank Select Signal Table)
[Bank Select Signal Table]
BA0
BA1
Bank 0
L
L
Bank 1
H
L
Bank 2
L
H
Bank 3
H
H
Remark: H: VIH. L: VIL.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDD2504AKTA-E | 256M bits DDR SDRAM (64M words x 4 bits) |
| EDD2508AKTA-5-E | 256M bits DDR SDRAM (32M words x 8 bits, DDR400) |
| EDD2508AKTA-5B-E | 256M bits DDR SDRAM (32M words x 8 bits, DDR400) |
| EDD2508AKTA-5C-E | 256M bits DDR SDRAM (32M words x 8 bits, DDR400) |
| EDD2508AKTA-5 | 256M bits DDR SDRAM (32M words x 8 bits, DDR400) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDD2504AKTA-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR SDRAM (64M words x 4 bits) |
| EDD2508AETA | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR SDRAM |
| EDD2508AETA-5B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR SDRAM |
| EDD2508AETA-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR SDRAM |
| EDD2508AETA-6B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR SDRAM |
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