參數(shù)資料
型號(hào): EDD1232AAFA
廠商: Elpida Memory, Inc.
英文描述: 128M bits DDR SDRAM (4M words x 32 bits)
中文描述: 128兆位DDR SDRAM內(nèi)存(4分字× 32位)
文件頁數(shù): 10/50頁
文件大?。?/td> 621K
代理商: EDD1232AAFA
EDD1232AABH
Data Sheet E0533E50 (Ver. 5.0)
10
Timing Parameter Measured in Clock Cycle
Number of clock cycle
tCK
6ns
7.5ns
Parameter
Symbol
min.
max.
min.
max.
Unit
Write to pre-charge command delay (same bank)
tWPD
4 + BL/2
3 + BL/2
tCK
Read to pre-charge command delay (same bank)
tRPD
BL/2
BL/2
tCK
Write to read command delay (to input all data)
tWRD
3 + BL/2
3 + BL/2
tCK
Burst stop command to write command delay
(CL = 2)
tBSTW
2
tCK
(CL = 2.5)
tBSTW
3
3
tCK
(CL = 3)
tBSTW
3
3
tCK
Burst stop command to DQ High-Z
(CL = 2)
tBSTZ
2
2
tCK
(CL = 2.5)
tBSTZ
2.5
2.5
2.5
2.5
tCK
(CL = 3)
tBSTZ
3
3
3
3
tCK
Read command to write command delay
(to output all data)
(CL = 2)
tRWD
2 + BL/2
tCK
(CL = 2.5)
tRWD
3 + BL/2
3 + BL/2
tCK
(CL = 3)
tRWD
3 + BL/2
3 + BL/2
tCK
Pre-charge command to High-Z
(CL = 2)
tHZP
2
2
tCK
(CL = 2.5)
tHZP
2.5
2.5
2.5
2.5
tCK
(CL = 3)
tHZP
3
3
3
3
tCK
Write command to data in latency
tWCD
1
1
1
1
tCK
Write recovery time
tWR
3
3
tCK
DM to data in latency
tDMD
0
0
0
0
tCK
Mode register set command cycle time
tMRD
2
2
tCK
Self refresh exit to non-read command
tSNR
12
10
tCK
Self refresh exit to read command
tSRD
200
200
tCK
Power down entry
tPDEN
1
1
1
1
tCK
Power down exit to command input
tPDEX
1
1
tCK
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