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參數(shù)資料
| 型號(hào)： | ECOG1 |
| 英文描述： | eCOG1 Microcontroller |
| 中文描述： | eCOG1微控制器 |
| 文件頁(yè)數(shù)： | 5/11頁(yè) |
| 文件大?。?/td> | 277K |
| 代理商： | ECOG1 |
PRELIMINARY
V3.1
www.cyantechnology.com
3
Host Control Port (HCP)
Provides direct access internal registers
of each USART
Custom serial protocols may be
emulated
Up to 255 symbols per frame
Parity may be automatically inserted or
tested at the end of each frame
Start bit edge detection
Tx/Rx interrupts
SPI
Multi-slave SPI system
Four slave select lines
Both master and slave roles
Programmable clock polarity and
clock/data phase
Smart Card Interface
ISO 7816 compatible smart card
interface
Multiprocessor support
Byte level support for T=0 and T=1
transmission protocols
Detection and generation of the
transmission error signal for T=0
protocol
Automatic retransmission of corrupted
bytes for T=0 protocol
Independent controls for power and
ground switching
Hardware state machine for power up,
reset and shutdown sequences
Consumer IR / IrDA
Programmable baud rates
Support for low rate (<115.2 kbps) IrDA
framing and modulation
Compatible with common ASK, PM,
PPM (e.g. RC-5) modulation schemes
Variable frame lengths up to 255 bits
Variable length multi-byte frames
Half duplex operation supported using
an integral transceiver frame duration
(maximum 1023 symbols) to separate
transmit and receive exchanges
Raw IR mode (software modem)
supported
Programmable start, stop, data length,
frame length and polarities
Programmable start and stop
sequences
Support for current and future frame
formats
Carrier frequency generation
I
2C
Two wire I2C compatible port
Address matching
ACK bit and wait state insertion
Multi-master arbitration
Supports 10-bit addressing and fast
mode
External Host Interface (EHI)
Provides a DMA interface to an external
host or FIFO
Memory mapped peripheral port
Supports master and slave mode timing
16/32-bit data bus
Request & Acknowledge control lines
Configurable master mode timing
Direct DMA connection into internal
SRAM (11-bit block address, max 256
byte block size)
Internal DMA controller supports circular
buffer and link list buffer models
8-bit external address with 16-bit data
3-bit external address with 32-bit data
Three control lines: chip select, direction
and wait
Configurable control line senses
Interrupt generated upon transfer
General Purpose I/O (GPIO)
29 memory mapped GPIO pins
Configured as Input, Output, bi-
directional
Directly drive or open drain outputs
Direct drive LEDs
Each input can generate an interrupt
External Interrupts
Any GPIO configured as an Input can
generate an interrupt
Level or edge sensitive interrupts
Parallel Interface (PIO)
Two 16-bit parallel data ports
Directly drive, open drain, or tri-state
outputs
Timers
16-bit Watch Dog Timer
16-bit Real Time Clock
24-bit Long Interval Timer
Two 16-bit PWMs CGT1 and CGT2
Two 16-bit General Purpose
Timers/event counters (GPT)
16-bit timer (CPT) with multiple event
capture registers
16-bit ripple counter
Most timers have pre-scalars
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