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參數(shù)資料
| 型號： | ECOG1 |
| 英文描述： | eCOG1 Microcontroller |
| 中文描述： | eCOG1微控制器 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大小： | 277K |
| 代理商： | ECOG1 |
V3.1
www.cyantechnology.com
1-Mar-2002
The eCOG1 microcontroller is a low-power microcontroller based on a 16-bit Harvard architecture
with a 24-bit word code linear address space (32Mbyte) and 16-bit word linear data address
space (128Kbytes). It is available in a 128-pin LQFP with or without the IntAct high-speed serial
interface. A comprehensive toolset and C Compiler are available.
0 to 25MHz 3.3V processor
Powerful arithmetic operations
Barrel Shifter
Harvard Architecture
64Kx16 Data Memory
16Mx16 Program Memory
Built in Emulator (eICE)
Low power operation
64Kbytes FLASH EPROM
4Kbytes SRAM
MMU
Power-saving code cache
Code security feature
External Host Interface
External Memory Interface
Fast Vectored Interrupts
Dual UART
Dual USART
Smart Card Interface
SPI
I2C
Consumer IR/IRDA
4 channel 12-bit A/D
Parallel Interface
5 Multi Purpose Timers
Watchdog Timer
Long Interval Timer
Real Time Clock
PWM timers
Temperature Sensor
Supply Voltage Sensor
Power-On Reset
General Purpose I/O
25MHz from watch XTAL
Interfaces to 8/16/32-bit parts
4KBytes
iRAM
Dual
UART
USART/SPI/IR
/IrDA/I2C/
Smart Card IF
IntAct
EHI
Switching Multiplexer
PWM
MMU
64K
Bytes
Flash
EPROM
Code
Cache
eCOG1
CPU Core
IRC
Temp
Sensor
EMI
PIF
GPIO
eICE
MUX
12 Bit
ADC
Power
On
Reset
eICE_miso
eICE_Clock
eICE_Load#
Interupt
Requests
Vin
Timers
System
Clock
Clock Inputs
External
Triggers
24 Bit
Addr/Data
8 Bit Data
16/32 Bit
Interface
29 Bit I/O
or Control
Up
Down
ChA
ChB
Data
Control
Vdd
Sensor
Stream
Register
Block
4
eICE_mosi
eICE_CS
Reset_In
Figure 1 – Internal Block Diagram
This document describes a device that is currently at pre-production status. Some specifications or descriptions may change.
PRELIMINARY
eCOG1 Microcontroller
Low Power Communications Processor
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