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參數(shù)資料
| 型號： | EBE20RE4AAFA |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 1 Rank) |
| 中文描述： | 2GB的注冊DDR2 SDRAM DIMM內(nèi)存（256M字× 72位，1個等級） |
| 文件頁數(shù)： | 15/22頁 |
| 文件大?。?/td> | 191K |
| 代理商： | EBE20RE4AAFA |
EBE20RE4AAFA
Data Sheet E0440E30 (Ver. 3.0)
15
AC Characteristics (TC = 0
°C
to +85
°
C, VDD, VDDQ = 1.8V ± 0.1V, VSS = 0V)
(DDR2 SDRAM Component Specification)
-5C
-4A
Frequency (Mbps)
533
400
Parameter
Symbol
min.
max.
min.
max.
Unit
Notes
/CAS latency
CL
4
5
3
5
tCK
Active to read or write command delay tRCD
15
15
ns
Precharge command period
Active to active/auto refresh command
time
DQ output access time from CK, /CK
tRP
15
15
ns
tRC
60
60
ns
tAC
500
+500
600
+600
ps
DQS output access time from CK, /CK tDQSCK
450
+450
500
+500
ps
CK high-level width
tCH
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
min.
(tCL, tCH)
3750
0.55
0.45
min.
(tCL, tCH)
5000
0.55
tCK
CK half period
tHP
ps
Clock cycle time
tCK
8000
8000
ps
DQ and DM input hold time
tDH
225
275
ps
5
DQ and DM input setup time
Control and Address input pulse width
for each input
DQ and DM input pulse width for each
input
Data-out high-impedance time from
CK,/CK
Data-out low-impedance time from
CK,/CK
DQS-DQ skew for DQS and associated
DQ signals
DQ hold skew factor
tDS
100
150
ps
4
tIPW
0.6
0.6
tCK
tDIPW
0.35
0.35
tCK
tHZ
tAC max.
tAC max.
ps
tLZ
tAC min.
tAC max.
tAC min.
tAC max.
ps
tDQSQ
300
350
ps
tQHS
400
450
ps
DQ/DQS output hold time from DQS
Write command to first DQS latching
transition
DQS input high pulse width
tQH
tHP – tQHS
tHP – tQHS
ps
tDQSS
WL
0.25
WL + 0.25
WL
0.25
WL + 0.25
tCK
tDQSH
0.35
0.35
tCK
DQS input low pulse width
tDQSL
0.35
0.35
tCK
DQS falling edge to CK setup time
tDSS
0.2
0.2
tCK
DQS falling edge hold time from CK
tDSH
0.2
0.2
tCK
Mode register set command cycle time tMRD
2
2
tCK
Write preamble setup time
tWPRES
0
0
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
Write preamble
tWPRE
0.25
0.25
tCK
Address and control input hold time
tIH
375
475
ps
5
Address and control input setup time
tIS
250
350
ps
4
Read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
Active to precharge command
tRAS
45
70000
45
70000
ns
Active to auto-precharge delay
Active bank A to active bank B
command period
tRAP
tRCD min.
tRCD min.
ns
tRRD
7.5
7.5
ns
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EBE20RE4AAFA-4A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 1 Rank) |
| EBE20RE4AAFA-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 1 Rank) |
| EBE20RE4ABFA | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR2 SDRAM DIMM |
| EBE20RE4ABFA-4A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR2 SDRAM DIMM |
| EBE20RE4ABFA-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2GB Registered DDR2 SDRAM DIMM |
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