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參數(shù)資料
| 型號： | E728-EDGE728 |
| 英文描述： | Very High-Speed Dual- and Quad-Channel ECL Delay Lines |
| 中文描述： | 極高速雙和四通道ECL延遲線 |
| 文件頁數(shù)： | 18/18頁 |
| 文件大小： | 133K |
| 代理商： | E728-EDGE728 |
9
2000 Semtech Corp.
www .semtech.com
HIGH-PERFORMANCE PRODUCTS – ATE
Edge728
Application Information
Power Up Initialization
Note: Mode 2 uses an SR flip-flop at the output stage;
mode 0 does not. Therefore, upon power-up in mode 2,
or when operating modes are being changed into mode
2, the SR flip-flop is in an indeterminate state and the
output may not reflect the input condition. A rising or falling
edge that propagates through the channel will correctly
reset the part. Therefore, in mode 2, a dummy edge should
be applied before calibration or real time execution.
Notice also that in mode 0 there are NO flip-flops. The
outputs will, therefore, always reflect the status of the
inputs.
PECL Operation
It is possible to use the part with positive voltage supplies.
GND becomes VCC and VEE becomes GND. All voltages
are then referenced off of the positive supply level.
Analog Voltage Inputs
The VWIDTH input has a normal operating range between
–0.1V and –1.1V, and the VDELAY input has a normal
operating range between –0.2V and –1.1V. However, the
on-board ESD diodes are rated to allow the direct
connection of a voltage DAC that can range from +7.5V
to –4V, through a resistance of
≥ 600, with no damage
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