參數(shù)資料
型號(hào)： E6420-EDGE6420
英文描述： Per-Pin Electronics Companion DAC
中文描述： 按針腳電子伴侶援
文件頁數(shù)： 6/29頁
文件大?。?/td> 244K
代理商： E6420-EDGE6420
14
2000 Semtech Corp.
www .semtech.com
HIGH-PERFORMANCE PRODUCTS – ATE
Edge6420
Circuit Description (continued)
Current Outputs
The TEST_MODE and SCAN_OUT pins on the Edge6420
are used in the same way as for voltage outputs. The
scan circuits for current outputs are shown in Figure 6.
The voltage measured at the SCAN_OUT pin, using the
configuration in Figure 6, for Group E and F current outputs
are as follows:
VSCAN_OUT_E = (RSENSE_E + RPAD) * IOUT_E
where:
RSENSE_E = 400 ± 30%
RPAD = 30 ± 30%
and
VSCAN_OUT_F = (RSENSE_F + RPAD) * IOUT_F
where:
RSENSE_F = 400 ± 30%
RPAD = 30 ± 30%
The typical "ON" resistance of the FET switch is 100 k
,
but can vary from 60 k
to 180 k as a function of process
and output voltage.
Notes when Using SCAN Feature with Multiple Chips
When multiple 6420s are used on a board, and it is desired
to gang the SCAN_OUT pins of these 6420s, or gang the
TEST_MODE inputs to one point, it is required for proper
functioning that the following rules be followed:
1)
If TEST_MODE inputs are ganged together,
SCAN_OUT cannot be ganged, or invalid results
will be observed at the SCAN_OUT pin. Hence,
each SCAN_OUT pin on a 6420 will have to be
measured separately.
2)
If SCAN_OUT is ganged, TEST_MODE pins cannot
be ganged together.
Figure 6. Current Output Scan Circuits
ADDRESS
DECODER
+
–
IOUT_CH0_0
TEST_MODE
SCAN_OUT
IDAC
+
–
IOUT_CH0_1
IDAC
+
–
IOUT_CH0_2
IDAC
CONNECT TO
VIRTUAL GROUND
CONNECT TO
VIRTUAL GROUND
NOTE: WHEN ADDRESS 64 IS INVOKED (PARALLEL LOAD), SCAN IS DISABLED.
CONNECT TO
VIRTUAL GROUND
R
SENSE
R
SENSE
R
PAD
R
PAD
R
PAD
R
SENSE
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