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參數(shù)資料
| 型號： | E6420-EDGE6420 |
| 英文描述： | Per-Pin Electronics Companion DAC |
| 中文描述： | 按針腳電子伴侶援 |
| 文件頁數(shù)： | 18/29頁 |
| 文件大?。?/td> | 244K |
| 代理商： | E6420-EDGE6420 |
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25
2000 Semtech Corp.
www .semtech.com
HIGH-PERFORMANCE PRODUCTS – ATE
Edge6420
AC Characteristics
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Figure 8. Shift Register Loading Timing Diagram
Figure 9. Central and Individual DAC Updating
Test conditions (unless otherwise specified): "Recommended Operating
Conditions".
Note 1:
Not production tested. Guaranteed by design and
characterization.
Note 2:
The max spec of 70% of TCK is not production tested.
Note 3:
CK24 refers to 24th rising clock edge, which corresponds
to a full shift register. Note that a falling CK24 edge is also
required for proper operation of circuit.
Note 4:
The 6420 is production tested at 55 MHz only, with 50%
duty cycle.
Note 5:
Duty cycle % shown refers to “high” duration of clock
in a period.
SDI
CK
CK1
CK24
Valid Data
A0
Valid Data
D15
TSU_SDI
THLD_SDI
CE
CK
UPDATE
CK24
CK1
THLD_CE
TSU_CE
TCK
THLD_UPDATE
TSU_UPDATE
Note: A 24th falling
CK edge is required for
DAC updating!
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