
 1059
SAM4CP [DATASHEET]
43051E–ATPL–08/14
E
Universal Synchronous Asynchronous Receiver Transmitter (USART)
‘MCK’ replaced by ‘peripheral clock’.
Section 36.2 “Embedded Characteristics” on page 738
 added ‘Digital Filter on Receive Line’
bullet.
Updated 
Figure 36-1
.
Updated information on RXIDLEV bit in 
Section 36.6.3.2 “Manchester Encoder” on page 746
and 
Section 36.7.21 “USART Manchester Configuration Register” on page 796
.
Updated 
Figure 36-36
.
Section 36.6.7.5 “Character Transmission” on page 767
 INACK replaced by WRDBT.
Section 36.7.3 “USART Mode Register” on page 774
 updated USART_MODE, USCLKS and
FILTER field descriptions.
Section 36.7.4 “USART Mode Register (SPI_MODE)” on page 777
 added CLKO bit.
Updated ENDRX, ENDTX, TXBUFE, and RXBUFF bit descriptions in 
“USART Interrupt
Enable Register” 
, 
“USART Interrupt Enable Register (SPI_MODE)” 
, 
“USART Interrupt
Disable Register” 
, 
“USART Interrupt Disable Register (SPI_MODE)” 
and 
“USART Channel
Status Register” 
.
Updated RXRDY, TXRDY, TXEMPTY, and CTSIC bit descriptions in 
“USART Channel Status
Register” 
.
Updated RXRDY, TXRDY, and TXEMPTY bit descriptions in 
“USART Channel Status
Register (SPI_MODE)” 
.
Section 36.7.18 “USART FI DI RATIO Register” on page 793
 FI_DI_RATIO field now 11 bits
wide.
Timer Counter (TC)
‘MCK’ replaced by ‘peripheral clock’.
Added 
Section 37.6.14.6 “Missing Pulse Detection and Auto-correction” on page 820
Section 37.7.14 “TC Block Mode Register” on page 841
 removed FILTER bit (register bit 19
now reserved). Added AUTOC bit and MAXCMP field.
Section 37.7.18 “TC QDEC Interrupt Status Register” on page 846
 added MPE bit.
Segment Liquid Crystal Display Controller (SLCDC)
Updated 
Section 39.5.2 “Power Management” on page 875
.
Revised 
Section 39.6.7 “Disabling the SLCDC” on page 881
(was “Disable Sequence”).
Section 39.8.8 “SLCDC Interrupt Mask Register” on page 897
 modified access to Read-only.
Analog-to-Digital Converter (ADC)
Added 
Table 40-2
 and 
Table 40-3
.
Advanced Encryption Standard (AES)
Section 41.5.2 “AES Mode Register” on page 956
 updated PROCDLY bit description.
Updated 
Figure 41-4
.
Updated 
Section 41.4.5 “Galois Counter Mode (GCM)” on page 947
.
Section 41.5.3 “AES Interrupt Enable Register” on page 958
, 
Section 41.5.4 “AES Interrupt
Disable Register” on page 959
, 
Section 41.5.5 “AES Interrupt Mask Register” on page 960
added TAGRDY bit.
Doc. Rev.
43051
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