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參數資料
| 型號： | DWP-20(2) |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | LOW-POWER DISSIPATION ADSL LINE DRIVER |
| 中文描述： | 低功耗ADSL線路驅動器 |
| 文件頁數： | 11/30頁 |
| 文件大小： | 1105K |
| 代理商： | DWP-20(2) |
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www.ti.com
6
100 k
5
4
3
2
1
0
1
2
3
f Frequency Hz
O
1 M
10 M
100 M
1 G
V
CC
=
±
5 V
Gain = 1
R
L
= 25
V
O
= 0.1 V
rms
Full Bias
R
F
= 1 k
R
F
= 1.2 k
R
F
= 2 k
6
5
4
3
2
1
0
1
2
3
f Frequency Hz
O
100 k
1 M
10 M
100 M
1 G
V
CC
=
±
5 V
Gain = 1
R
L
= 100
V
O
= 0.1 V
rms
Full Bias
R
F
= 1 k
R
F
= 1.2 k
R
F
= 2 k
7
100 k
8
9
10
11
12
13
14
15
16
f Frequency Hz
O
1 M
10 M
100 M
V
CC
=
±
5 V
Gain = 5
R
L
= 25
V
O
= 0.1 V
rms
Full Bias
R
F
= 750
R
F
= 500
R
F
= 2 k
7
100 k
8
9
10
11
12
13
14
15
16
f Frequency Hz
O
1 M
10 M
100 M
V
CC
=
±
5 V
Gain = 5
R
L
= 100
V
O
= 0.1 V
rms
Full Bias
R
F
= 750
R
F
= 500
R
F
= 2 k
R
F
= 1 k
12
13
14
15
16
17
18
19
20
21
f Frequency Hz
O
100 k
1 M
10 M
100 M
V
=
±
5 V
Gain = 10
R
L
= 25
V
lO
= 0.1 V
rms
Full Bias
R
F
= 500
R
F
= 2 k
R
F
= 1 k
12
13
14
15
16
17
18
19
20
21
f Frequency Hz
O
100 k
1 M
10 M
100 M
V
CC
=
±
5 V
Gain = 10
R
L
= 25
V
= 0.1 V
rms
Full Bias
R
F
= 500
R
F
= 2 k
R
F
= 1 k
0.01
0.1
1
10
100
1000
f Frequency Hz
Z
Shutdown
Mid Bias
Low Bias
Full Bias
100 k
1 M
10 M
100 M
V
CC
=
±
12 V
Gain = 10
R
L
= 500
0
100
200
300
400
500
0
5
Output Voltage Vpp
10
15
20
SR+
SR
S
5
10
15
20
25
3
9
13
Supply Voltage +/Vcc
T
Ta = 25 deg.C
Icc+ (Full)
Icc (Full)
Icc+ (Mid)
Icc (Mid)
A
Icc+ (Low)
Icc (Low)
Icc (SD)
Icc+ (SD)
5
7
11
15
THS6182
SLLS544G–SEPTEMBER 2002–REVISED NOVEMBER 2004
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
Figure 32.
Figure 33.
Figure 34.
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
Figure 35.
Figure 36.
Figure 37.
CLOSED LOOP OUTPUT
IMPEDANCE
vs
FREQUENCY
SLEW RATE
vs
OUTPUT VOLTAGE
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
Figure 38.
Figure 39.
Figure 40.
11
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