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    參數(shù)資料
    型號(hào): DSPIC30F6013T-20E/PF
    廠商: Microchip Technology
    文件頁(yè)數(shù): 10/228頁(yè)
    文件大小: 0K
    描述: IC DSPIC MCU/DSP 132K 80TQFP
    產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
    標(biāo)準(zhǔn)包裝: 1,000
    系列: dsPIC™ 30F
    核心處理器: dsPIC
    芯體尺寸: 16-位
    速度: 20 MIPS
    連通性: CAN,I²C,SPI,UART/USART
    外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LVD,POR,PWM,WDT
    輸入/輸出數(shù): 68
    程序存儲(chǔ)器容量: 132KB(44K x 24)
    程序存儲(chǔ)器類(lèi)型: 閃存
    EEPROM 大?。?/td> 2K x 8
    RAM 容量: 6K x 8
    電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
    數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
    振蕩器型: 內(nèi)部
    工作溫度: -40°C ~ 125°C
    封裝/外殼: 80-TQFP
    包裝: 帶卷 (TR)
    配用: DM300024-ND - KIT DEMO DSPICDEM 1.1
    AC164314-ND - MODULE SKT FOR PM3 80PF
    其它名稱(chēng): DSPIC30F6013T20EP
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    2006 Microchip Technology Inc.
    DS70117F-page 105
    dsPIC30F6011/6012/6013/6014
    16.2
    Enabling and Setting Up UART
    16.2.1
    ENABLING THE UART
    The UART module is enabled by setting the UARTEN
    bit in the UxMODE register (where x = 1 or 2). Once
    enabled, the UxTX and UxRX pins are configured as an
    output and an input respectively, overriding the TRIS
    and LATCH register bit settings for the corresponding
    I/O port pins. The UxTX pin is at logic ‘1’ when no
    transmission is taking place.
    16.2.2
    DISABLING THE UART
    The UART module is disabled by clearing the UARTEN
    bit in the UxMODE register. This is the default state
    after any Reset. If the UART is disabled, all I/O pins
    operate as port pins under the control of the latch and
    TRIS bits of the corresponding port pins.
    Disabling the UART module resets the buffers to empty
    states. Any data characters in the buffers are lost and
    the baud rate counter is reset.
    All error and status flags associated with the UART
    module are reset when the module is disabled. The
    URXDA, OERR, FERR, PERR, UTXEN, UTXBRK and
    UTXBF bits are cleared, whereas RIDLE and TRMT
    are
    set.
    Other
    control
    bits,
    including
    ADDEN,
    URXISEL<1:0>, UTXISEL, as well as the UxMODE
    and UxBRG registers, are not affected.
    Clearing the UARTEN bit while the UART is active will
    abort all pending transmissions and receptions and
    reset the module as defined above. Re-enabling the
    UART will restart the UART in the same configuration.
    16.2.3
    SETTING UP DATA, PARITY AND
    STOP BIT SELECTIONS
    Control bits PDSEL<1:0> in the UxMODE register are
    used to select the data length and parity used in the
    transmission. The data length may either be 8 bits with
    even, odd or no parity, or 9 bits with no parity.
    The STSEL bit determines whether one or two Stop bits
    will be used during data transmission.
    The default (power-on) setting of the UART is 8 bits, no
    parity and 1 Stop bit (typically represented as 8, N, 1).
    16.3
    Transmitting Data
    16.3.1
    TRANSMITTING IN 8-BIT DATA
    MODE
    The following steps must be performed in order to
    transmit 8-bit data:
    1.
    Set up the UART:
    First, the data length, parity and number of Stop
    bits must be selected. Then, the transmit and
    receive interrupt enable and priority bits are
    setup in the UxMODE and UxSTA registers.
    Also, the appropriate baud rate value must be
    written to the UxBRG register.
    2.
    Enable the UART by setting the UARTEN bit
    (UxMODE<15>).
    3.
    Set the UTXEN bit (UxSTA<10>), thereby
    enabling a transmission.
    4.
    Write the byte to be transmitted to the lower byte
    of UxTXREG. The value will be transferred to the
    Transmit Shift register (UxTSR) immediately
    and the serial bit stream will start shifting out
    during the next rising edge of the baud clock.
    Alternatively, the data byte may be written while
    UTXEN = 0, following which, the user may set
    UTXEN. This will cause the serial bit stream to
    begin immediately because the baud clock will
    start from a cleared state.
    5.
    A transmit interrupt will be generated, depend-
    ing on the value of the interrupt control bit
    UTXISEL (UxSTA<15>).
    16.3.2
    TRANSMITTING IN 9-BIT DATA
    MODE
    The sequence of steps involved in the transmission of
    9-bit data is similar to 8-bit transmission, except that a
    16-bit data word (of which the upper 7 bits are always
    clear) must be written to the UxTXREG register.
    16.3.3
    TRANSMIT BUFFER (UXTXB)
    The transmit buffer is 9 bits wide and 4 characters
    deep. Including the Transmit Shift register (UxTSR),
    the user effectively has a 5-deep FIFO (First-In, First-
    Out) buffer. The UTXBF status bit (UxSTA<9>)
    indicates whether the transmit buffer is full.
    If a user attempts to write to a full buffer, the new data
    will not be accepted into the FIFO, and no data shift will
    occur within the buffer. This enables recovery from a
    buffer overrun condition.
    The FIFO is reset during any device Reset but is not
    affected when the device enters or wakes up from a
    power-saving mode.
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