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參數(shù)資料
| 型號(hào)： | DSPIC30F2012-30I/ML |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 29/66頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSPIC MCU/DSP 12K 28QFN |
| 產(chǎn)品培訓(xùn)模塊： | Serial Communications using dsPIC30F I2C Serial Communications using dsPIC30F SPI Serial Communications using dsPIC30F UART dsPIC30F 12 bit ADC - Part 2 dsPIC30F Addressing Modes - Part 1 dsPIC30F Architecture - Part 1 dsPIC30F DSP Engine & ALU dsPIC30F Interrupts dsPIC30F Motor Control PWM dsPIC Timers Asynchronous Stimulus dsPIC30F Addressing Modes - Part 2 dsPIC30F Architecture - Part 2 dsPIC30F 12-bit ADC Part 1 |
| 標(biāo)準(zhǔn)包裝： | 61 |
| 系列： | dsPIC™ 30F |
| 核心處理器： | dsPIC |
| 芯體尺寸： | 16-位 |
| 速度： | 30 MIP |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 20 |
| 程序存儲(chǔ)器容量： | 12KB（4K x 24） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.5 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 10x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 28-VQFN 裸露焊盤 |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 650 (CN2011-ZH PDF) |
| 配用： | AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE |
| 其它名稱： | DSPIC30F201230IML |
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2010 Microchip Technology Inc.
DS70102K-page 35
dsPIC30F Flash Programming Specification
11.2.2
REGOUT SERIAL INSTRUCTION
EXECUTION
The REGOUT control code allows for data to be
extracted from the device in ICSP mode. It is used to
clock the contents of the VISI register out of the device
over the PGD pin. Once the REGOUT control code is
received, eight clock cycles are required to process the
command. During this time, the CPU is held idle. After
these eight cycles, an additional 16 cycles are required
to clock the data out (see Figure 11-3).
The REGOUT instruction is unique because the PGD
pin is an input when the control code is transmitted to
the device. However, once the control code is
processed, the PGD pin becomes an output as the VISI
register is shifted out. After the contents of the VISI are
shifted out, PGD becomes an input again as the state
machine holds the CPU idle until the next 4-bit control
code is shifted in.
Note:
Once the contents of VISI are shifted out,
the dsPIC DSC device maintains PGD
as an output until the first rising edge of
the next clock is received.
FIGURE 11-1:
PROGRAM ENTRY AFTER RESET
FIGURE 11-2:
SIX SERIAL EXECUTION
FIGURE 11-3:
REGOUT SERIAL EXECUTION
P4
23
12
3
23 24
1
2
3
4
P1
PGC
P4a
PGD
24-bit Instruction Fetch
Execute 24-bit Instruction,
Execute PC – 1,
14
00
0
Fetch SIX Control Code
Fetch Next Control Code
4
5
6
7
8
18 19 202122
17
LSB X
X
X MSB
PGD = Input
P2
P3
P1B
P1A
56
7
00
0
00
0
89
00
P4
23
1
2
3
23 24
1
2
3
4
P1
PGC
P4a
PGD
24-bit Instruction Fetch
Execute 24-bit Instruction,
Execute PC – 1,
14
00
0
00
0
Fetch SIX Control Code
Fetch Next Control Code
4
5
6
7
8
18 19 202122
17
LSB X
X
X MSB
PGD = Input
P2
P3
P1a
P1b
12
3
4
1
2
7
8
PGC
P4
PGD
PGD = Input
Execute Previous Instruction,
CPU Held In Idle
Shift Out VISI Register <15:0>
P5
PGD = Output
12
3
12
3
4
P4a
11
13
15 16
14
12
No Execution Takes Place,
Fetch Next Control Code
0
00
0
PGD = Input
MSb
1
2
3
4
1
45
6
LSb
14
13
12
...
11
10
0
Fetch REGOUT Control Code
0
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