
External Bus Asynchronous Timing
56F827 Technical Data
29
3.7 External Bus Asynchronous Timing
Table 13. External Bus Asynchronous Timing
1, 2
Operating Conditions:
V
SSIO
=V
SS
= V
SSA
= 0V, V
DDA
=V
DDIO
=3.0–3.6V, V
DD
= 2.25–2.75V, T
A
= –40
°
to +85
°
C, C
L
≤
50pF, f
op
= 80MHz
1.
T = Clock Period. For 80MHz operation, T = 12.5ns.
2.
Parameters listed are guaranteed by design.
Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and
To calculate the required access time for an external memory for any frequency < 80MHz, use this formula:
Top = Clock period @ desired operating frequency
WS = Number of wait states
Memory Access Time = (Top*WS) + (Top- 11.5)
Characteristic
Symbol
Min
Max
Unit
Address Valid to WR Asserted
t
AWR
6.5
—
ns
WR Width Asserted
Wait states = 0
Wait states > 0
t
WR
7.5
(T*WS) + 7.5
—
—
ns
ns
WR Asserted to D0–D15 Out Valid
t
WRD
—
T + 4.2
ns
Data Out Hold Time from WR Deasserted
t
DOH
4.8
—
ns
Data Out Set Up Time to WR Deasserted
Wait states = 0
Wait states > 0
t
DOS
2.2
(T*WS) + 6.4
—
—
ns
ns
RD Deasserted to Address Not Valid
t
RDA
0
—
ns
Address Valid to RD Deasserted
Wait states = 0
Wait states > 0
t
ARDD
18.7
(T*WS) + 18.7
—
ns
ns
Input Data Hold to RD Deasserted
t
DRD
0
—
ns
RD Assertion Width
Wait states = 0
Wait states > 0
t
RD
19
(T*WS) + 19
—
—
ns
ns
Address Valid to Input Data Valid
Wait states = 0
Wait states > 0
t
AD
—
—
1
(T*WS) + 1
ns
ns
Address Valid to RD Asserted
t
ARDA
-4.4
—
ns
RD Asserted to Input Data Valid
Wait states = 0
Wait states > 0
t
RDD
—
—
2.4
(T*WS) + 2.4
ns
ns
WR Deasserted to RD Asserted
t
WRRD
6.8
—
ns
RD Deasserted to RD Asserted
t
RDRD
0
—
ns
WR Deasserted to WR Asserted
t
WRWR
14.1
—
ns
RD Deasserted to WR Asserted
t
RDWR
12.8
—
ns
F
Freescale Semiconductor, Inc.
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n
.