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參數(shù)資料
| 型號： | DSP56F826BU80E |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | 16-bit Digital Signal Controllers |
| 中文描述： | 16位數(shù)字信號控制器 |
| 文件頁數(shù)： | 16/56頁 |
| 文件大?。?/td> | 700K |
| 代理商： | DSP56F826BU80E |
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56F826 Technical Data, Rev. 14
16
Freescale Semiconductor
MISO
(GPIOF6)
86
Input/Output
Input/Output
SPI Master In/Slave Out (MISO)
—This serial data pin is an input to a master
device and an output from a slave device. The MISO line of a slave device is
placed in the high-impedance state if the slave device is not selected.
Port F GPIO
—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
After reset, the default state is MISO.
SS
(GPIOF7)
87
Input
Input/Output
SPI Slave Select
—In master mode, this pin is used to arbitrate multiple masters.
In slave mode, this pin is used to select the slave.
Port F GPIO
—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
After reset, the default state is SS.
TXD0
(SCLK0)
97
Output
Input/Output
Transmit Data (TXD0)
—transmit data output
SPI Serial Clock—
In master mode, this pin serves as an output, clocking slaved
listeners. In slave mode, this pin serves as the data clock input.
After reset, the default state is SCI output.
RXD0
(MOSI0)
96
Input
Input/Output
Receive Data (RXD0)
— receive data input
SPI Master Out/Slave In
—This serial data pin is an output from a master
device, and an input to a slave device. The master device places data on the
MOSI line one half-cycle before the clock edge the slave device uses to latch the
data.
After reset, the default state is SCI input.
TXD1
(MISO0)
93
Output
Input/Output
Transmit Data (TXD1)
—transmit data output
SPI Master In/Slave Out—
This serial data pin is an input to a master device and
an output from a slave device. The MISO line of a slave device is placed in the
high-impedance state if the slave device is not selected.
After reset, the default state is SCI output.
RXD1
(SS0)
92
Input
(Schmitt)
Input
Receive Data (RXD1)
— receive data input
SPI Slave Select
—In master mode, this pin is used to arbitrate multiple masters.
In slave mode, this pin is used to select the slave.
After reset, the default state is SCI input.
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name
Pin No.
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSP56F826E | 16-bit Digital Signal Controllers |
| DSP56F826 | 16-bit Hybrid Controller(16位混合控制器) |
| DSP56F827E | 16-bit Digital Signal Controllers |
| DSP56F827FG80 | 16-bit Digital Signal Controllers |
| DSP56F827FG80E | 16-bit Digital Signal Controllers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP56F826BU80E | 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor |
| DSP56F826BU80E | 制造商:Freescale Semiconductor 功能描述:DSP LQFP100 3.6V |
| DSP56F826D | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Preliminary Technical Data DSP56F826 16-bit Digital Signal Processor |
| DSP56F826E | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| DSP56F826EVM | 功能描述:開發(fā)板和工具包 - 其他處理器 Evaluation Kit For DSP56F826 RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
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