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參數(shù)資料
| 型號： | DSP56F807VF80E |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | 16-bit Digital Signal Controllers |
| 中文描述： | 16位數(shù)字信號控制器 |
| 文件頁數(shù)： | 12/60頁 |
| 文件大?。?/td> | 522K |
| 代理商： | DSP56F807VF80E |
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56F807 Technical Data Technical Data, Rev. 15
12
Freescale Semiconductor
2.5 Interrupt and Program Control Signals
Table 2-7 Data Bus Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
16
D0–D15
Input/O
utput
Tri-stated
Data Bus
— D0–D15 specify the data for external program or data
memory accesses. D0–D15 are tri-stated when the external bus is
inactive. Internal pullups may be active.
Table 2-8 Bus Control Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
PS
Output
Tri-stated
Program Memory Select
—PS is asserted low for external program
memory access.
1
DS
Output
Tri-stated
Data Memory Select
—DS is asserted low for external data memory
access.
1
WR
Output
Tri-stated
Write Enable
—WR is asserted during external memory write cycles.
When WR is asserted low, pins D0–D15 become outputs and the device
puts data on the bus. When WR is deasserted high, the external data is
latched inside the external device. When WR is asserted, it qualifies the
A0–A15, PS, and DS pins. WR can be connected directly to the WE pin of
a Static RAM.
1
RD
Output
Tri-stated
Read Enable
—RD is asserted during external memory read cycles. When
RD is asserted low, pins D0–D15 become inputs and an external device is
enabled onto the device’s data bus. When RD is deasserted high, the
external data is latched inside the device. When RD is asserted, it qualifies
the A0–A15, PS, and DS pins. RD can be connected directly to the OE pin
of a Static RAM or ROM.
Table 2-9 Interrupt and Program Control Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
IRQA
Input
(Schmitt)
Input
External Interrupt Request A
—The IRQA input is a synchronized
external interrupt request that indicates that an external device is
requesting service. It can be programmed to be level-sensitive or
negative-edge-triggered.
1
IRQB
Input
(Schmitt)
Input
External Interrupt Request B
—The IRQB input is an external
interrupt request that indicates that an external device is requesting
service. It can be programmed to be level-sensitive or
negative-edge-triggered.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSP56F807 | 16-bit Hybrid Controller(16位混合控制器) |
| DSP56F826BU80 | 16-bit Digital Signal Controllers |
| DSP56F826BU80E | 16-bit Digital Signal Controllers |
| DSP56F826E | 16-bit Digital Signal Controllers |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP56F807VF80E | 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC |
| DSP56F807VF80J | 制造商:Freescale Semiconductor 功能描述:DSP 16BIT - Trays |
| DSP56F826 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| DSP56F826-827UM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor Users Manual |
| DSP56F826-827UM/D | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:56F827 16-bit Hybrid Controller |
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