
56854 Technical Data, Rev. 6
4
Freescale Semiconductor
Part 1 Overview
1.1 56854 Features
1.1.1
Digital Signal Processing Core
Efficient 16-bit engine with dual Harvard architecture
120 Million Instructions Per Second (MIPS) at 120MHz core frequency
Single-cycle 16
×
16-bit parallel Multiplier-Accumulator (MAC)
Four (4) 36-bit accumulators including extension bits
16-bit bidirectional shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three (3) internal address buses and one (1) external address bus
Four (4) internal data buses and one (1) external data bus
Instruction set supports both DSP and controller functions
Four (4) hardware interrupt levels
Five (5) software interrupt levels
Controller-style addressing modes and instructions for compact code
Efficient C Compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/Enhanced OnCE debug programming interface
1.1.2
Memory
Harvard architecture permits up to three (3) simultaneous accesses to program and data memory
On-Chip Memory
— 16K
×
16-bit Program SRAM
— 16K
×
16-bit Data SRAM
— 1K
×
16-bit Boot ROM
Off-Chip Memory Expansion (EMI)
— Access up to 2M words of program memory or up to 8M words of data memory
— Chip Select Logic for glue-less interface to ROM and SRAM
1.1.3
Peripheral Circuits for 56854
General Purpose 16-bit Quad Timer*
Two (2) Serial Communication Interfaces (SCI)*
Serial Peripheral Interface (SPI) Port*
Enhanced Synchronous Serial Interface (ESSI) module*
Computer Operating Properly (COP)/Watchdog Timer