參數(shù)資料
型號(hào)： DSP5685xUM
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 16-bit Digital Signal Controllers
中文描述： 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù)： 18/60頁(yè)
文件大?。?/td> 836K
代理商： DSP5685XUM
56854 Technical Data, Rev. 6
18
Freescale Semiconductor
15
MODA
GPIOH0
Input
Input/Output
Mode Select (MODA)
—During the bootstrap process MODA
selects one of the eight bootstrap modes.
Port H GPIO (0)
—This pin is a General Purpose I/O (GPIO) pin
after the bootstrap process has completed.
16
MODB
GPIOH1
Input
Input/Output
Mode Select (MODB)
—During the bootstrap process MODB
selects one of the eight bootstrap modes.
Port H GPIO (1)
—This pin is a General Purpose I/O (GPIO) pin
after the bootstrap process has completed.
17
MODC
GPIOH2
Input
Input/Output
Mode Select (MODC)
—During the bootstrap process MODC
selects one of the eight bootstrap modes.
Port H GPIO (2)
—This pin is a General Purpose I/O (GPIO) pin
after the bootstrap process has completed.
35
RESET
Input
Reset (RESET)
—This input is a direct hardware reset on the
processor. When RESET is asserted low, the device is initialized
and placed in the Reset state. A Schmitt trigger input is used for
noise immunity. When the RESET pin is deasserted, the initial chip
operating mode is latched from the MODA, MODB, and MODC
pins.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware reset is required and it is necessary
not to reset the JTAG/Enhanced OnCE module. In this case, assert
RESET, but do not assert TRST.
34
RSTO
Output
Reset Output (RSTO)
—This output is asserted on any reset
condition (external reset, low voltage, software or COP).
65
RXD0
GPIOE0
Input
Input/Output
Serial Receive Data 0 (RXD0)
—This input receives byte-oriented
serial data and transfers it to the SCI 0 receive shift register.
Port E GPIO (0)
—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
66
TXD0
GPIOE1
Output(Z)
Input/Output
Serial Transmit Data 0 (TXD0)
—This signal transmits data from
the SCI 0 transmit data register.
Port E GPIO (1)
—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
94
RXD1
GPIOE2
Input
Input/Output
Serial Receive Data 1 (RXD1)
—This input receives byte-oriented
serial data and transfers it to the SCI 1 receive shift register.
Port E GPIO (2)
—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)
Pin No.
Signal Name
Type
Description
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