
56855 Technical Data, Rev. 6
38
Freescale Semiconductor
Table 4-11 ESSI Slave Mode1 Switching Characteristics
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz
1. Slave mode is externally generated clocks and frame syncs
Parameter
Symbol
Min
Typ
Max
Units
SCK frequency
fs
—
152
2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for a 120MHz part.
MHz
SCK period3
tSCKW
66.7
—
ns
SCK high time
tSCKH
33.44
——
ns
SCK low time
tSCKL
33.44
——
ns
Output clock rise/fall time
—
4
—
ns
Delay from SCK high to SC2 (bl) high - Slave5
tTFSBHS
-1
—
29
ns
Delay from SCK high to SC2 (wl) high - Slave5
tTFSWHS
-1
—
29
ns
Delay from SC0 high to SC1 (bl) high - Slave5
tRFSBHS
-1
—
29
ns
Delay from SC0 high to SC1 (wl) high - Slave5
tRFSWHS
-1
—
29
ns
Delay from SCK high to SC2 (bl) low - Slave5
tTFSBLS
-29
—
29
ns
Delay from SCK high to SC2 (wl) low - Slave5
tTFSWLS
-29
—
29
ns
Delay from SC0 high to SC1 (bl) low - Slave5
tRFSBLS
-29
—
29
ns
Delay from SC0 high to SC1 (wl) low - Slave5
tRFSWLS
-29
—
29
ns
SCK high to STD enable from high impedance - Slave
tTXES
——
15
ns
SCK high to STD valid - Slave
tTXVS
4—
15
ns
SC2 high to STD enable from high impedance (first bit) - Slave
tFTXES
4—
15
ns
SC2 high to STD valid (first bit) - Slave
tFTXVS
4—
15
ns
SCK high to STD not valid - Slave
tTXNVS
4—
15
ns
SCK high to STD high impedance - Slave
tTXHIS
4—
15
ns
SRD Setup time before SC0 low - Slave
tSS
4—
—
ns
SRD Hold time after SC0 low - Slave
tHS
4—
—
ns
Synchronous Operation (in addition to standard external clock parameters)
SRD Setup time before SCK low - Slave
tTSS
4—
—
ns
SRD Hold time after SCK low - Slave
tTHS
4—
—
ns