參數(shù)資料
型號(hào)： DSP56855BUE
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 22/52頁(yè)
文件大?。?/td> 0K
描述： IC DSP 16BIT 120MHZ 100-LQFP
標(biāo)準(zhǔn)包裝： 90
系列： 568xx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 120MHz
連通性： EBI/EMI，SCI，SSI
外圍設(shè)備： DMA，POR，WDT
輸入/輸出數(shù)： 18
程序存儲(chǔ)器容量： 48KB（24K x 16）
程序存儲(chǔ)器類型： SRAM
RAM 容量： 24K x 16
電壓 - 電源 (Vcc/Vdd)： 1.62 V ~ 1.98 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
包裝： 托盤
Reset, Stop, Wait, Mode Select, and Interrupt Timing
56855 Technical Data, Rev. 6
Freescale Semiconductor
29
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction execution
in the interrupt service routine
tIDM
18T
—
ns
tIDM -FAST
14T
—
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
tIG
18T
—
ns
tIG -FAST
14T
—
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State4
tIRI
22T
—
ns
tIRI -FAST
18T
—
Delay from IRQA Assertion (exiting Stop) to External
Data Memory5
tIW
1.5T
—
ns
Delay from IRQA Assertion (exiting Wait) to External
Data Memory
Fast6
Normal7
tIF
18T
22ET
—
ns
RSTO pulse width8
normal operation
internal reset mode
tRSTO
128ET
8ET
—
1. In the formulas, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns.
2. Parameters listed are guaranteed by design.
3. At reset, the PLL is disabled and bypassed. The part is then put into Run mode and tclk assumes the period of the source clock,
txtal, textal or tosc.
4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not
the minimum required so that the IRQA interrupt is accepted.
5. The interrupt instruction fetch is visible on the pins only in Mode 3.
6. Fast stop mode:
Fast stop recovery applies when external clocking is in use (direct clocking to XTAL) or when fast stop mode recovery is re-
quested (OMR bit 6 is set to 1). In both cases the PLL and the master clock are unaffected by stop mode entry. Recovery takes one
less cycle and tclk will continue same value it had before stop mode was entered.
7. Normal stop mode:
As a power saving feature, normal stop mode disables and bypasses the PLL. Stop mode will then shut down the master clock,
recovery will take an extra cycle (to restart the clock), and tclk will resume at the input clock source rate.
8. ET = External Clock period, For an external crystal frequency of 8MHz, ET=125 ns.
Table 1. Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 2 (Continued)
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz
Characteristic
Symbol
Min
Max
Unit
See Figure
相關(guān)PDF資料
PDF描述
DSP56857BUE IC DSP 16BIT 120MHZ 100-LQFP
DSP56858FVE IC DSP 16BIT 120MHZ 144-LQFP
DSP56F801FA80E IC DSP 60MHZ 16KB FLASH 48-LQFP
DSP56F802TA80E IC DSP 60MHZ 16KB FLASH 32-LQFP
DSP56F803BU80E IC DSP 80MHZ 64KB FLASH 100LQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56855E 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers
DSP56855PB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:56855 Digital Signal Processor Product Brief
DSP56856 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Digitial Signal Controller
DSP56857 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers
DSP56857BU120 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 120Mhz/120MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*