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參數(shù)資料
| 型號(hào)： | DSP1628 |
| 英文描述： | TVS 400W 60V BIDIRECT SMA |
| 中文描述： | 澄清，串行I /設(shè)備的DSP1620/27/28/29 O控制注冊(cè)說(shuō)明 |
| 文件頁(yè)數(shù)： | 34/114頁(yè) |
| 文件大小： | 804K |
| 代理商： | DSP1628 |
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Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
32
Lucent Technologies Inc.
4 Hardware Architecture
(continued)
ECCP Internal Memory-Mapped Registers:
Internal memory-mapped registers are defined in the ECCP address space
for control and status purposes and to hold data. A summary of the contents of these registers is given in Table 13.
Table 13. Memory-Mapped Registers
Address
Register
Register Bit Field
0x0000—0x007F
Next State Register
NS[0:63]—24-bit words split across two ad-
dress locations
Reserved
Bit 31:16 is addressed by even address.
Bit 31:24 zero.
Bit 23:16 most significant byte of path cost.
Bit 15: 0 is addressed by odd address.
Bit 15:0 lower 2 bytes of path cost.
Bit 31:16 is addressed by even address.
Bit 31:24 zero.
Bit 23:16 most significant byte of path cost.
Bit 15:0 is addressed by odd address.
Bit 15:0 lower 2 bytes of path cost.
Bit 5:0 is used.
Bit 15:6 reserved.
Bit 0 is soft decision select.
Bit 1 is Manhattan/Euclidean branch metric select.
Bit 2 is soft/hard decision select.
Bit 3 is reserved.
Bit 7:4 is reserved.
Bit 10:8 is code rate select.
Bit 11 is reserved.
Bit 14:12 is constraint length select.
Bit 15 is reserved.
Bit 5:0 is used.
Bit 15:6 is reserved.
Convolutional decoding case:
Bit 7:0 is reserved.
Bit 15:8 is S5.
MLSE equalization case:
Bit 7:0 is HQ5.
Bit 15:8 is HI5.
Convolutional decoding case:
Bit 7:0 is reserved.
Bit 15:8 is S4.
MLSE equalization case:
Bit 7:0 is HQ4.
Bit 15:8 is HI4.
Convolutional decoding case:
Bit 7:0 is reserved.
Bit 15:8 is S3.
MLSE equalization case:
Bit 7:0 is HQ3.
Bit 15:8 is HI3.
Convolutional decoding case:
Bit 7:0 is reserved.
Bit 15:8 is S2.
MLSE equalization case:
Bit 7:0 is HQ2.
Bit 15:8 is HI2.
0x0080—0x01FF
0x0200—0x027F
Present State Register
PS[0:63]—24-bit words split across two ad-
dress locations
Reserved
0x0280—0x03FF
0x400
Current Symbol Pointer
SYC
Control Register
ECON
0x401
0x402
Traceback Length Register
TBLR
Received Symbol/Channel Tap Register
S5H5
0x403
0x404
Received Symbol/Channel Tap Register
S4H4
0x405
Received Symbol/Channel Tap Register
S3H3
0x406
Received Symbol/Channel Tap Register
S2H2
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