參數(shù)資料
型號(hào)： DS87C520-WCL
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 26/43頁(yè)
文件大?。?/td> 0K
描述： IC MCU EPROM/ROM 33MHZ HS 40CDIP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 10
系列： 87C
核心處理器： 8051
芯體尺寸： 8-位
速度： 33MHz
連通性： EBI/EMI，SIO，UART/USART
外圍設(shè)備： 電源故障復(fù)位，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 16KB（16K x 8）
程序存儲(chǔ)器類(lèi)型： EPROM，UV
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 40-CDIP（0.600"，15.24mm）窗口
包裝： 管件
其它名稱(chēng)： DS87C520WCL
DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers
32 of 43
AC ELECTRICAL CHARACTERISTICS (Note 1)
33 MHz
VARIABLE CLOCK
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
External Oscillator
0
33
0
33
Oscillator
Frequency
External Crystal
1/tCLCL
1
33
1
33
MHz
ALE Pulse Width
tLHLL
40
1.5tCLCL-5
ns
Port 0 Address Valid to ALE Low
tAVLL
10
0.5tCLCL-5
ns
Address Hold after ALE Low
tLLAX1
(Note 2)
ns
ALE Low to Valid Instruction In
tLLIV
43
2.5tCLCL-33
ns
ALE Low to PSEN Low
tLLPL
4
0.5tCLCL-11
ns
PSEN
Pulse Width
tPLPH
55
2tCLCL-5
ns
PSEN
Low to Valid Instruction In
tPLIV
37
2tCLCL-24
ns
Input Instruction Hold after PSEN
tPXIX
0
ns
Input Instruction Float after PSEN
tPXIZ
26
tCLCL-5
ns
Port 0 Address to Valid Instruction In
tAVIV1
59
3tCLCL-32
ns
Port 2 Address to Valid Instruction In
tAVIV2
68
3.5tCLCL-38
ns
PSEN
Low to Address Float
tPLAZ
(Note 2)
ns
Note 1:
All parameters apply to both commercial and industrial temperature range operation unless otherwise noted.
Specifications to -40°C are guaranteed by design and are not production tested. AC electrical characteristics are not
100% tested, but are characterized and guaranteed by design. All signals characterized with load capacitance of 80pF
except Port 0, ALE,
PSEN, RD, and WR with 100pF. Interfacing to memory devices with float times (turn off times)
over 25ns may cause contention. This will not damage the parts, but will cause an increase in operating current.
Specifications assume a 50% duty cycle for the oscillator. Port 2 and ALE timing will change in relation to duty cycle
variation.
Note 2:
Address is driven strongly until ALE falls, and is then held in a weak latch until overdriven externally.
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