參數(shù)資料
型號: DS80C400-FNY+
廠商: Maxim Integrated Products
文件頁數(shù): 62/97頁
文件大小: 0K
描述: IC MCU 75MHZ 16MB HP 100-LQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 90
系列: 80C
核心處理器: 8051
芯體尺寸: 8-位
速度: 75MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),SIO,UART/USART
外圍設備: 電源故障復位,WDT
輸入/輸出數(shù): 64
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: ROM
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 3.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-LQFP
包裝: 托盤
配用: DS80C400-KIT#-ND - EVAL KIT FOR DS80C400
其它名稱: DS80C400+FNY
DS80C400+FNY+
DS80C400+FNY+-ND
DS80C400+FNY-ND
DS80C400 Network Microcontroller
65 of 97
Transmit/Receive Status Words
For each attempt made by the MAC to receive or transmit packet data, the BCU writes a 32-bit transmit or receive
status word back to the first word of the starting page for the packet. This word provides status information needed
by the CPU to determine when and what action should be taken.
Transmit Status Word
Bit Names:
31
RETRY
24
23
16
15
HBF
COL_CNT [3:0]
OLTCOL
DFR
8
7
NODAT
XCOL
LTCOL
XDFR
LSCRS
NOCRS
JABTO
ABORT
0
RETRY, Packet Retry. This bit indicates that the current transmit packet has to be retried because of a collision on
the bus. The application has to restart the transmission of the frame when this bit is set to 1. When this bit is reset,
it indicates that the transmission of the current frame is completed. The success or failure to transmit a frame is
indicated by the framed aborted (ABORT) bit.
HBF, Heart-Beat Fail. This bit is only meaningful for ENDEC mode. This bit is not valid if the NODAT or XFDR bit
is set.
0 = heart-beat collision check successful
1 = heart-beat collision check failed
COL_CNT [3:0], Collision Count. These four bits indicate the number of collisions that occurred before the frame
was transmitted. Collision count is valid only in half-duplex mode and it is not valid when the excessive collisions
(XCOL) bit is set.
OLTCOL, Late Collision Observed. This bit is only valid in half-duplex mode and is always set if the late collision
abort (LTCOL) bit is set in the status word.
0 = no late collisions observed
1 = late collision (collision after the first time slot) observed.
DFR, Deferred. This bit is only valid in half-duplex mode.
0 = no deferral required for the frame transmission attempt
1 = MAC had to defer while waiting to transmit because the carrier was not idle
NODAT, Underrun
0 = transmit frame was not aborted due to data underrun
1 = transmit frame aborted because the MAC did not have sufficient data to complete the current frame
transmission
XCOL, Excessive Collisions. This bit is only valid in half-duplex mode.
0 = transmit frame was not aborted due to excessive collisions
1 = transmit frame aborted because of excessive collisions (16 transmit attempts unless DRTY = 1)
LTCOL, Late Collision. This bit is only valid in half-duplex mode.
0 = transmit frame was not aborted due to a late collision
1 = transmit frame aborted due to collision occurring after the collision window of 64 Bytes. This bit is not valid if the
NODAT bit is set.
XDFR, Excessive Deferral. This bit is only valid in half-duplex mode when the MAC control register bit DFR is set.
0 = transmit frame was not aborted due to excessive deferral
1 = transmit frame aborted due to deferral of over 24,288 bit times
LSCRS, Loss of Carrier. This bit is only valid in half-duplex mode.
0 = transmit frame was not aborted due to loss of carrier
1 = transmit frame aborted due to loss of carrier (CRS = 0 during the frame transmission)
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