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參數資料
| 型號： | DS80C390 |
| 英文描述： | Dual CAN High-Speed Microprocessor |
| 中文描述： | 雙CAN高速微處理器 |
| 文件頁數： | 11/58頁 |
| 文件大?。?/td> | 5486K |
| 代理商： | DS80C390 |
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DS80C390
11 of 58
110199
ARITHMETIC ACCELERATOR SEQUENCING
Divide (32/16 or 16/16)
Load MA with dividend LSB.
Load MA with dividendLSB+1
*
Load MA with dividend LSB+2
*
Load MA with dividend MSB.
Load MB with divisor LSB.
Load MB with divisor MSB.
Poll the MST bit until cleared
(9 machine cycles).
Read MA to retrieve the quotient MSB.
Read MA to retrieve the quotient LSB+2.
Read MA to retrieve the quotient LSB+1.
Read MA to retrieve the quotient LSB.
Read MB to retrieve the remainder MSB.
Read MB to retrieve the remainder LSB.
*Not performed for 16 bit numerator.
Shift Right/Left
Load MA with data LSB.
Load MA with data LSB+1.
Load MA with data LSB+2.
Load MA with data MSB.
Configure MCNT0 register as required
Poll the MST bit until cleared.
(9 machine cycles)
Read MA for result MSB.
Read MA for result LSB+2.
Read MA for result LSB+1.
Read MA for result LSB.
Multiply (16x16)
Load MB with multiplier LSB.
Load MB with multiplier MSB.
Load MA with multiplicand LSB.
Load MA with multiplicand MSB.
Poll the MST bit until cleared
(6 machine cycles).
Read MA for product MSB.
Read MA for product LSB+2.
Read MA for product LSB+1.
Read MA for product LSB.
Normalize
Load MA with data LSB.
Load MA with data LSB+1.
Load MA with data LSB+2.
Load MA with data MSB.
Configure MCNT0 register as required.
Poll the MST bit until cleared
(9 machine cycles).
Read MA for mantissa MSB.
Read MA for mantissa LSB+2.
Read MA for mantissa LSB+1.
Read MA for mantissa LSB.
Read MCNT0.4-MCNT0.0 for exponent.
40-BIT ACCUMULATOR
The accelerator also incorporates an automatic accumulator function, permitting the implementation of
multiply-and-accumulate and divide-and-accumulate functions without any additional delay. Each time
the accelerator is used for a multiply or divide operation, the result is transparently added to a 40-bit
accumulator. This can greatly increase speed of DSP and other high-level math operations.
The accumulator can be accessed any time the Multiply/Accumulate Status Flag (MCNT1;D2h) is
cleared. The accumulator is initialized by performing five writes to the Multiplier C Register (MC;D5h),
LSB first. The 40-bit accumulator can be read by performing five reads of the Multiplier C Register,
MSB first.
相關PDF資料 |
PDF描述 |
|---|---|
| DS80C390-QNR | Dual CAN High-Speed Microprocessor |
| DS80C390-FCR | Dual CAN High-Speed Microprocessor |
| DS80C390-FNR | Dual CAN High-Speed Microprocessor |
| DS80C390-QCR | Dual CAN High-Speed Microprocessor |
| DS80C410 | Network Microcontrollers with Ethernet and CAN |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DS80C390_00 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:High-Speed Microcontroller User’s Guide Supplement |
| DS80C390_05 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Dual CAN High-Speed Microprocessor |
| DS80C390+FCR | 制造商:Maxim Integrated Products 功能描述:MICRO DUAL CAN LQFP PB-FREE - Trays |
| DS80C390+QCR | 制造商:Maxim Integrated Products 功能描述:MICRO DUAL CAN PLCC PB-FREE - Rail/Tube |
| DS80C390+QNR | 制造商:Maxim Integrated Products 功能描述:MICRO DUAL CAN PLCC IND PB-FREE - Rail/Tube |
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