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參數資料
| 型號： | DS4M200P+33 |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 6/7頁 |
| 文件大小： | 0K |
| 描述： | IC OSC CLOCK 200MHZ 10-LCCC |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 27 |
| 類型： | 時鐘振蕩器 |
| 頻率： | 200MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 電流 - 電源： | 74mA |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 10-LCCC 裸露焊盤 |
| 包裝： | 管件 |
| 供應商設備封裝： | 10-LCCC |
| 安裝類型： | 表面貼裝 |
DS4M125/DS4M133/DS4M200
Detailed Description
The DS4M125/DS4M133/DS4M200 consist of an oscil-
lator designed to oscillate with a fundamental-mode
crystal and a PLL to synthesize the base frequency with
its ±5% deviations. The output interface is either
LVPECL or LVDS.
The ±5% frequency deviation is controlled through a
three-level margining select (MS) pin. This three-state
input pin accepts a three-level voltage signal to control
the output frequency. In a low-level state, the output
frequency is set to the nominal frequency. When set to
a high-level state, the frequency output is set to the
nominal frequency plus 5%. When set to the mid-level
state, the frequency output is equal to the nominal fre-
quency minus 5%. The MS pin has an internal 100k
Ω
pulldown resistor. When the pin is left floating, the
devices output a nominal frequency.
The devices are available with either LVDS or LVPECL
output drivers. When the OE signal is low, the LVPECL
output driver is turned off and the output voltage goes
to the PECL_BIAS level of VCC - 2.0V, while the LVDS
outputs are a logical one. The OE pin has an internal
100k
Ω pullup resistor. When the pin is left floating, the
device output is active.
3.3V Margining Clock Oscillator with
LVPECL/LVDS Output
6
_______________________________________________________________________________________
DIVP
DIVFB
X1
X2
THREE-
STATE
PHASE
DET
FILTER
LC-VCO
THREE-
LEVEL
DECODER
DIVOUT
OUTSELN
FREQUENCY SELECTION
OUTDRV
VCC
OE
OUTP
OUTN
MS
GND
DS4M125/
DS4M133/
DS4M200
Figure 1. Functional Diagram
OE
OUTP
tP1A
tPA1
0.7 x VCC
0.3 x VCC
OUTN
Figure 2. LVDS Output Timing Diagram When OE Is Enabled
and Disabled
OE
OUTP
PECL_BIAS
OUTN
0.7 x VCC
0.3 x VCC
tPAZ
tPZA
Figure 3. LVPECL Output Timing Diagram When OE Is Enabled
and Disabled
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