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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | DS3508E+T&R |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋佹暩(sh霉)锛� | 8/14闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC GAMMA BUFFER 8CH 20-TSSOP |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 2,500 |
| 鎳�(y墨ng)鐢細 | TFT-LCD 闈㈡澘锛氫冀鐟珐娌栧櫒 |
| 闆昏矾鏁�(sh霉)锛� | 8 |
| 闆绘祦 - 闆绘簮锛� | 2mA |
| 闆绘祦 - 杓稿嚭 / 閫氶亾锛� | 6mA |
| 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� | 9 V ~ 15.5 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 20-TSSOP锛�0.173"锛�4.40mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 20-TSSOP |
| 鍖呰锛� | 甯跺嵎 (TR) |
DS3508
I2C, 8-Channel Gamma Buffer with EEPROM
_______________________________________________________________________________________
3
OUTPUT ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V; VDD = 15.5V, TA = -45掳C to +95掳C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Gamma DAC Resolution
8
Bits
Integral Nonlinearity Error
TA = +25掳C (Note 4)
-1.25
+1.25
LSB
Differential Nonlinearity Error
TA = +25掳C (Note 5)
-0.5
+0.5
LSB
Output Voltage Range:
GM1鈥揋M4
VHM
VHH
V
Output Voltage Range:
GM5鈥揋M8
VLL
VLM
V
ROUT (GM1鈥揋M8)
ROUT
(Notes 6, 7)
20
k
Amplifier Offset
TA = +25掳C (Note 8)
-35
+35
mV
I2C ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -45掳C to +95掳C, timing referenced to VIL(MAX) and VIH(MIN).) (Figure 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
fSCL
(Note 9)
0
400
kHz
Low Period of SCL
tLOW
Measured at VIL
1.3
渭s
High Period of SCL
tHIGH
Measured at VIH
0.6
渭s
Bus Free Time Between STOP
and START Conditions
tBUF
1.3
渭s
START Setup Time
tSU:STA
SCL rising through VIH to SDA falling
through VIH
0.6
渭s
Hold Time (Repeated) START
Condition
tHD:STA
SDA falling through VIL to SCL falling
through VIH
0.6
渭s
Data Hold Time
tHD:DAT
0
0.9
渭s
Data Setup Time
tSU:DAT
100
ns
A0 Setup Time
tSU:A
Before START
0.6
渭s
A0 Hold Time
tHD:A
After STOP
0.6
渭s
SDA and SCL Rise Time
tR
(Note 10)
20 + (0.1 x CB)
300
ns
SDA and SCL Fall Time
tF
(Note 10)
20 + (0.1 x CB)
300
ns
STOP Setup Time
tSU:STO
0.6
渭s
SDA and SCL Capacitive
Loading
CB
(Note 10)
400
pF
EEPROM Write Time
tW
(Note 11)
20
ms
SCL Falling Edge to SDA Output
Data Valid
tAA
SCL falling through VIL to SDA exit
0.3鈥�0.7 x VCC window
900
ns
Output Data Hold
tDH
SCL falling through VIL until SDA in
0.3鈥�0.7 x VCC window
0
ns
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