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參數(shù)資料
| 型號： | DS32C35-33#T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 7/22頁 |
| 文件大小： | 0K |
| 描述： | IC RTC ACCURATE I2C 3.3V 20-SOIC |
| 產(chǎn)品變化通告： | Product Discontinuation 28/Nov/2011 |
| 標準包裝： | 1,000 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，F(xiàn)RAM，閏年，方波輸出，TCXO/晶體 |
| 存儲容量： | 8KB |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 3.63 V |
| 電壓 - 電源，電池： | 2.3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 帶卷 (TR) |
DS32B35/DS32C35
Accurate I2C RTC with Integrated
TCXO/Crystal/FRAM
____________________________________________________________________
15
Status Register (0Fh)
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit
indicates that the oscillator either is stopped or was
stopped for some period and may be used to judge the
validity of the timekeeping data. This bit is set to logic 1
any time that the oscillator stops. The following are
examples of conditions that can cause the OSF bit to
be set:
1) The first time power is applied.
2) The voltages present on both VCC and VBAT are
insufficient to support oscillation.
3) The EOSC bit is turned off in battery-backed mode.
4) External influences on the crystal (i.e., noise, leak-
age, etc.).
This bit remains at logic 1 until written to logic 0.
Bit 3: Enable 32kHz Output (EN32kHz). This bit con-
trols the status of the 32kHz pin. When set to logic 1,
the 32kHz pin is enabled and outputs a 32.768kHz
square-wave signal. When set to logic 0, the 32kHz pin
goes to a high-impedance state. The initial power-up
state of this bit is logic 1, and a 32.768kHz square-wave
signal appears at the 32kHz pin after a VCC is applied to
the device.
Bit 2: Busy (BSY). This bit indicates the device is busy
executing TCXO functions. It goes to logic 1 when the
conversion signal to the temperature sensor is asserted
and then is cleared when the device is in the 1-minute
idle state. When active, the BSY signal prevents the
CONV signal from aborting the execution of the TCXO
algorithm and starting a new execution of TCXO function.
Bit 1: Alarm 2 Flag (A2F). A logic 1 in the alarm 2 flag
bit indicates that the time matched the alarm 2 regis-
ters. If the A2IE bit is logic 1 and the INTCN bit is set to
logic 1, the INT/SQW pin is also asserted. A2F is
cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.
Bit 0: Alarm 1 Flag (A1F). A logic 1 in the alarm 1 flag
bit indicates that the time matched the alarm 1 regis-
ters. If the A1IE bit is logic 1 and the INTCN bit is set to
logic 1, the INT/SQW pin is also asserted. A1F is
cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.
Aging Offset Register (10h)
The Aging Offset register provides an 8-bit code to add
to the codes in the capacitance array registers. The
code is encoded in two’s complement. One LSB repre-
sents one small capacitor to be switched in or out of
the capacitance array at the crystal pins.
The change in ppm per LSB is different at different tem-
peratures. The frequency vs. temperature curve is dis-
torted by the values used in this register. At +23°C, one
LSB typically provides approximately 0.1ppm change
in frequency.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Sign
Data
Aging Offset (10h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OSF
0
EN32kHz
BSY
A2F
A1F
Status Register (0Fh)
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