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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | DS3232SN# |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋佹暩(sh霉)锛� | 8/19闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC RTC I2C W/TCXO 20-SOIC |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 45 |
| 椤炲瀷锛� | 鏅傞悩/鏃ユ |
| 鐗归粸锛� | 璀﹀牨鍣�锛岄枏骞达紝鏂规尝杓稿嚭锛孴CXO/鏅堕珨 |
| 瀛樺劜瀹归噺锛� | 236B |
| 鏅傞枔鏍煎紡锛� | HH:MM:SS锛�12/24 灏忔檪锛� |
| 鏁�(sh霉)鎿�(j霉)鏍煎紡锛� | YY-MM-DD-dd |
| 鎺ュ彛锛� | I²C锛�2 绶氫覆鍙� |
| 闆绘簮闆诲锛� | 2.3 V ~ 5.5 V |
| 闆诲 - 闆绘簮锛岄浕姹狅細 | 2.3 V ~ 5.5 V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 20-SOIC锛�0.295"锛�7.50mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 20-SOIC W |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 1434 (CN2011-ZH PDF) |
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I2C Serial Data Bus
The DS3232 supports a bidirectional I2C bus and data
transmission protocol. A device that sends data onto the
bus is defined as a transmitter and a device receiving
data is defined as a receiver. The device that controls the
message is called a master. The devices that are con-
trolled by the master are slaves. The bus must be con-
trolled by a master device that generates the serial clock
(SCL), controls the bus access, and generates the START
and STOP conditions. The DS3232 operates as a slave
on the I2C bus. Connections to the bus are made through
the SCL input and open-drain SDA I/O lines. Within the
bus specifications, a standard mode (100kHz maximum
clock rate) and a fast mode (400kHz maximum clock rate)
are defined. The DS3232 works in both modes.
The following bus protocol has been defined (Figure 2):
Data transfer may be initiated only when the bus is
not busy.
During data transfer, the data line must remain stable
whenever the clock line is high. Changes in the data
line while the clock line is high are interpreted as
control signals.
Accordingly, the following bus conditions have been
defined:
Bus not busy: Both data and clock lines remain
high.
Start data transfer: A change in the state of the
data line from high to low, while the clock line is high,
defines a START condition.
Stop data transfer: A change in the state of the data
line from low to high, while the clock line is high,
defines a STOP condition.
Data valid: The state of the data line represents
valid data when, after a START condition, the data
line is stable for the duration of the high period of the
clock signal. The data on the line must be changed
during the low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number
of data bytes transferred between the START and
the STOP conditions is not limited, and is determined
by the master device. The information is transferred
byte-wise and each receiver acknowledges with a
ninth bit.
Acknowledge: Each receiving device, when
addressed, is obliged to generate an acknowledge
after the reception of each byte. The master device
must generate an extra clock pulse, which is associ-
ated with this acknowledge bit.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge-related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the
last byte that has been clocked out of the slave. In
this case, the slave must leave the data line high to
enable the master to generate the STOP condition.
Figures 3 and 4 detail how data transfer is accom-
plished on the I2C bus. Depending upon the state of
the R/W bit, two types of data transfer are possible:
Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is
Extremely Accurate I2C RTC with
Integrated Crystal and SRAM
SDA
SCL
IDLE
1鈥�7
8
9
1鈥�7
8
9
1鈥�7
8
9
START
CONDITION
STOP CONDITION
REPEATED START
SLAVE
ADDRESS
R/W
ACK
DATA
ACK/
NACK
DATA
MSB FIRST
MSB
LSB
MSB
LSB
REPEATED IF MORE BYTES
ARE TRANSFERRED
Figure 2. I2C Data Transfer Overview
DS3232
16
Maxim Integrated
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| AD5273BRJZ100-R7 | IC POT DGTL 1K 64POS SOT23 |
| VI-B21-MY-F4 | CONVERTER MOD DC/DC 12V 50W |
| DS1744W-120+ | IC RTC RAM Y2K 3.3V 120NS 28EDIP |
| VI-B21-MY-F3 | CONVERTER MOD DC/DC 12V 50W |
| DS1744-70+ | IC RTC RAM Y2K 5V 70NS 28-EDIP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| DS3232SN# | 鍔熻兘鎻忚堪:瀵︽檪鏅傞悩 Integrated RTC/TCXO/Crystal RoHS:鍚� 鍒堕€犲晢:Microchip Technology 鍔熻兘:Clock, Calendar. Alarm RTC 绺界窔鎺ュ彛:I2C 鏃ユ湡鏍煎紡:DW:DM:M:Y 鏅傞枔鏍煎紡:HH:MM:SS RTC 瀛樺劜瀹归噺:64 B 闆绘簮闆诲-鏈€澶�:5.5 V 闆绘簮闆诲-鏈€灏�:1.8 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:Through Hole 灏佽 / 绠遍珨:PDIP-8 灏佽:Tube |
| DS3232SN#T&R | 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪: 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:EXTREMELY ACCURATE I2C RTC 20SOIC W - Tape and Reel 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:IC RTC W/TCXO 20-SOIC |
| DS3232SN#T&R | 鍔熻兘鎻忚堪:瀵︽檪鏅傞悩 Integrated RTC/TCXO/Crystal RoHS:鍚� 鍒堕€犲晢:Microchip Technology 鍔熻兘:Clock, Calendar. Alarm RTC 绺界窔鎺ュ彛:I2C 鏃ユ湡鏍煎紡:DW:DM:M:Y 鏅傞枔鏍煎紡:HH:MM:SS RTC 瀛樺劜瀹归噺:64 B 闆绘簮闆诲-鏈€澶�:5.5 V 闆绘簮闆诲-鏈€灏�:1.8 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:Through Hole 灏佽 / 绠遍珨:PDIP-8 灏佽:Tube |
| DS3232SN#-W | 鍔熻兘鎻忚堪:瀵︽檪鏅傞悩 RoHS:鍚� 鍒堕€犲晢:Microchip Technology 鍔熻兘:Clock, Calendar. Alarm RTC 绺界窔鎺ュ彛:I2C 鏃ユ湡鏍煎紡:DW:DM:M:Y 鏅傞枔鏍煎紡:HH:MM:SS RTC 瀛樺劜瀹归噺:64 B 闆绘簮闆诲-鏈€澶�:5.5 V 闆绘簮闆诲-鏈€灏�:1.8 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:Through Hole 灏佽 / 绠遍珨:PDIP-8 灏佽:Tube |
| DS3234 | 鍒堕€犲晢:MAXIM 鍒堕€犲晢鍏ㄧū:Maxim Integrated Products 鍔熻兘鎻忚堪:Extremely Accurate SPI Bus RTC with Integrated Crystal and SRAM |
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