Extremely Accurate I2C RTC with Integrated Crystal and SRAM Dat" />
參數(shù)資料
型號: DS3232SN#
廠商: Maxim Integrated Products
文件頁數(shù): 16/19頁
文件大?。?/td> 0K
描述: IC RTC I2C W/TCXO 20-SOIC
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 45
類型: 時鐘/日歷
特點: 警報器,閏年,方波輸出,TCXO/晶體
存儲容量: 236B
時間格式: HH:MM:SS(12/24 小時)
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 2.3 V ~ 5.5 V
電壓 - 電源,電池: 2.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 20-SOIC W
包裝: 管件
產(chǎn)品目錄頁面: 1434 (CN2011-ZH PDF)
Extremely Accurate I2C RTC with
Integrated Crystal and SRAM
Data Transfer on I2C Serial Bus
SCL
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
SDA
STOP
START
REPEATED
START
tBUF
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tHD:STA
tSP
tSU:STA
tHIGH
tR
tF
tLOW
Note 2: Limits at -40°C are guaranteed by design and not production tested.
Note 3: All voltages are referenced to ground.
Note 4: ICCA—SCL clocking at max frequency = 400kHz.
Note 5: Current is the averaged input current, which includes the temperature conversion current.
Note 6: The RST pin has an internal 50k
Ω (nominal) pullup resistor to VCC.
Note 7: After this period, the first clock pulse is generated.
Note 8: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal)
to bridge the undefined region of the falling edge of SCL.
Note 9: The maximum tHD:DAT needs only to be met if the device does not stretch the low period (tLOW) of the SCL signal.
Note 10: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT
≥ 250ns must then be met. This
is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the
low period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns
before the SCL line is released.
Note 11: CB—total capacitance of one bus line in pF.
Note 12: Minimum operating frequency of the I2C interface is imposed by the timeout period.
Note 13: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of
0V
≤ VCC ≤ VCC(MAX) and 2.3V ≤ VBAT ≤ 3.4V.
Note 14: This delay only applies if the oscillator is enabled and running. If the EOSC bit is 1, tREC is bypassed and RST immediately
goes high.
WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode may
cause loss of data.
DS3232
6
Maxim Integrated
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