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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | DS3231SN# |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋佹暩(sh霉)锛� | 6/20闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC RTC W/TCXO 16-SOIC |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 椤炲瀷锛� | 鏅傞悩/鏃ユ |
| 鐗归粸锛� | 璀﹀牨鍣�锛岄枏骞�锛屾柟娉㈣几鍑猴紝TCXO/鏅堕珨 |
| 鏅傞枔鏍煎紡锛� | HH:MM:SS锛�12/24 灏忔檪锛� |
| 鏁�(sh霉)鎿�(j霉)鏍煎紡锛� | YY-MM-DD-dd |
| 鎺ュ彛锛� | I²C锛�2 绶氫覆鍙� |
| 闆绘簮闆诲锛� | 2.3 V ~ 5.5 V |
| 闆诲 - 闆绘簮锛岄浕姹狅細 | 2.3 V ~ 5.5 V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 16-SOIC锛�0.295"锛�7.50mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 16-SOIC W |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 1434 (CN2011-ZH PDF) |
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Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
14
Maxim Integrated
DS3231
Status Register (0Fh)
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit
indicates that the oscillator either is stopped or was
stopped for some period and may be used to judge the
validity of the timekeeping data. This bit is set to logic 1
any time that the oscillator stops. The following are exam-
ples of conditions that can cause the OSF bit to be set:
1) The first time power is applied.
2) The voltages present on both VCC and VBAT are
insufficient to support oscillation.
3) The
EOSC bit is turned off in battery-backed mode.
4) External influences on the crystal (i.e., noise, leak-
age, etc.).
This bit remains at logic 1 until written to logic 0.
Bit 3: Enable 32kHz Output (EN32kHz). This bit con-
trols the status of the 32kHz pin. When set to logic 1, the
32kHz pin is enabled and outputs a 32.768kHz square-
wave signal. When set to logic 0, the 32kHz pin goes to
a high-impedance state. The initial power-up state of
this bit is logic 1, and a 32.768kHz square-wave signal
appears at the 32kHz pin after a power source is
applied to the DS3231 (if the oscillator is running).
Bit 2: Busy (BSY). This bit indicates the device is busy
executing TCXO functions. It goes to logic 1 when the
conversion signal to the temperature sensor is asserted
and then is cleared when the device is in the 1-minute
idle state.
Bit 1: Alarm 2 Flag (A2F). A logic 1 in the alarm 2 flag
bit indicates that the time matched the alarm 2 regis-
ters. If the A2IE bit is logic 1 and the INTCN bit is set to
logic 1, the
INT/SQW pin is also asserted. A2F is
cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.
Bit 0: Alarm 1 Flag (A1F). A logic 1 in the alarm 1 flag
bit indicates that the time matched the alarm 1 regis-
ters. If the A1IE bit is logic 1 and the INTCN bit is set to
logic 1, the
INT/SQW pin is also asserted. A1F is
cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.
Aging Offset
The aging offset register takes a user-provided value to
add to or subtract from the codes in the capacitance
array registers. The code is encoded in two鈥檚 comple-
ment, with bit 7 representing the sign bit. One LSB rep-
resents one small capacitor to be switched in or out of
the capacitance array at the crystal pins. The aging off-
set register capacitance value is added or subtracted
from the capacitance value that the device calculates
for each temperature compensation. The offset register
is added to the capacitance array during a normal tem-
perature conversion, if the temperature changes from
the previous conversion, or during a manual user con-
version (setting the CONV bit). To see the effects of the
aging register on the 32kHz output frequency immedi-
ately, a manual conversion should be started after each
aging register change.
Positive aging values add capacitance to the array,
slowing the oscillator frequency. Negative values
remove capacitance from the array, increasing the
oscillator frequency.
The change in ppm per LSB is different at different
temperatures. The frequency vs. temperature curve is
shifted by the values used in this register. At +25掳C,
one LSB typically provides about 0.1ppm change in
frequency.
Use of the aging register is not needed to achieve the
accuracy as defined in the EC tables, but could be
used to help compensate for aging at a given tempera-
ture. See the
Typical Operating Characteristics section
for a graph showing the effect of the register on accu-
racy over temperature.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME:
Sign
Data
POR:
0
Aging Offset (10h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME:
OSF
0
EN32kHz
BSY
A2F
A1F
POR:
1
0
1
X
Status Register (0Fh)
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| DS3231SN# | 鍔熻兘鎻忚堪:瀵︽檪鏅傞悩 Integrated RTC/TCXO/Crystal RoHS:鍚� 鍒堕€犲晢:Microchip Technology 鍔熻兘:Clock, Calendar. Alarm RTC 绺界窔鎺ュ彛:I2C 鏃ユ湡鏍煎紡:DW:DM:M:Y 鏅傞枔鏍煎紡:HH:MM:SS RTC 瀛樺劜瀹归噺:64 B 闆绘簮闆诲-鏈€澶�:5.5 V 闆绘簮闆诲-鏈€灏�:1.8 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:Through Hole 灏佽 / 绠遍珨:PDIP-8 灏佽:Tube |
| DS3231SN#T&R | 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:DS3231 16P SOIC ACC RTC 33V IND 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:REAL TIME CLOCK SERL 16SOIC W - Tape and Reel 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:IC RTC W/TCXO 16-SOIC 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:Real Time Clock Integrated RTC/TCXO/Crystal |
| DS3231SN#T&R | 鍔熻兘鎻忚堪:瀵︽檪鏅傞悩 Integrated RTC/TCXO/Crystal RoHS:鍚� 鍒堕€犲晢:Microchip Technology 鍔熻兘:Clock, Calendar. Alarm RTC 绺界窔鎺ュ彛:I2C 鏃ユ湡鏍煎紡:DW:DM:M:Y 鏅傞枔鏍煎紡:HH:MM:SS RTC 瀛樺劜瀹归噺:64 B 闆绘簮闆诲-鏈€澶�:5.5 V 闆绘簮闆诲-鏈€灏�:1.8 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:Through Hole 灏佽 / 绠遍珨:PDIP-8 灏佽:Tube |
| DS3231SN/T&R | 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:REAL TIME CLOCK SERL 16SOIC W - Tape and Reel 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:Real Time Clock Integrated RTC/TCXO/Crystal |
| DS3231SN/T&R | 鍔熻兘鎻忚堪:瀵︽檪鏅傞悩 Integrated RTC/TCXO/Crystal RoHS:鍚� 鍒堕€犲晢:Microchip Technology 鍔熻兘:Clock, Calendar. Alarm RTC 绺界窔鎺ュ彛:I2C 鏃ユ湡鏍煎紡:DW:DM:M:Y 鏅傞枔鏍煎紡:HH:MM:SS RTC 瀛樺劜瀹归噺:64 B 闆绘簮闆诲-鏈€澶�:5.5 V 闆绘簮闆诲-鏈€灏�:1.8 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�:Through Hole 灏佽 / 绠遍珨:PDIP-8 灏佽:Tube |
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