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鍨嬭櫉(h脿o)锛� DS3231SN#
寤犲晢锛� Maxim Integrated Products
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鎻忚堪锛� IC RTC W/TCXO 16-SOIC
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渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 16-SOIC W
鍖呰锛� 绠′欢
鐢�(ch菐n)鍝佺洰閷勯爜(y猫)闈細 1434 (CN2011-ZH PDF)
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
12
Maxim Integrated
DS3231
the binary-coded decimal (BCD) format. The DS3231
can be run in either 12-hour or 24-hour mode. Bit 6 of
the hours register is defined as the 12- or 24-hour
mode select bit. When high, the 12-hour mode is
selected. In the 12-hour mode, bit 5 is the
AM/PM bit
with logic-high being PM. In the 24-hour mode, bit 5 is
the 20-hour bit (20鈥�23 hours). The century bit (bit 7 of
the month register) is toggled when the years register
overflows from 99 to 00.
The day-of-week register increments at midnight.
Values that correspond to the day of week are user-
defined but must be sequential (i.e., if 1 equals
Sunday, then 2 equals Monday, and so on). Illogical
time and date entries result in undefined operation.
When reading or writing the time and date registers, sec-
ondary (user) buffers are used to prevent errors when
the internal registers update. When reading the time and
date registers, the user buffers are synchronized to the
internal registers on any START and when the register
pointer rolls over to zero. The time information is read
from these secondary registers, while the clock contin-
ues to run. This eliminates the need to reread the regis-
ters in case the main registers update during a read.
The countdown chain is reset whenever the seconds regis-
ter is written. Write transfers occur on the acknowledge
from the DS3231. Once the countdown chain is reset, to
avoid rollover issues the remaining time and date registers
must be written within 1 second. The 1Hz square-wave out-
put, if enabled, transitions high 500ms after the seconds
data transfer, provided the oscillator is already running.
Alarms
The DS3231 contains two time-of-day/date alarms.
Alarm 1 can be set by writing to registers 07h to 0Ah.
Alarm 2 can be set by writing to registers 0Bh to 0Dh.
The alarms can be programmed (by the alarm enable
and INTCN bits of the control register) to activate the
INT/SQW output on an alarm match condition. Bit 7 of
each of the time-of-day/date alarm registers are mask
bits (Table 2). When all the mask bits for each alarm
are logic 0, an alarm only occurs when the values in the
timekeeping registers match the corresponding values
stored in the time-of-day/date alarm registers. The
alarms can also be programmed to repeat every sec-
ond, minute, hour, day, or date. Table 2 shows the pos-
sible settings. Configurations not listed in the table will
result in illogical operation.
The DY/
DT bits (bit 6 of the alarm day/date registers)
control whether the alarm value stored in bits 0 to 5 of
that register reflects the day of the week or the date of
the month. If DY/
DT is written to logic 0, the alarm will
be the result of a match with date of the month. If
DY/
DT is written to logic 1, the alarm will be the result of
a match with day of the week.
When the RTC register values match alarm register set-
tings, the corresponding Alarm Flag 鈥楢1F鈥� or 鈥楢2F鈥� bit is
set to logic 1. If the corresponding Alarm Interrupt
Enable 鈥楢1IE鈥� or 鈥楢2IE鈥� is also set to logic 1 and the
INTCN bit is set to logic 1, the alarm condition will acti-
vate the
INT/SQW signal. The match is tested on the
once-per-second update of the time and date registers.
Table 2. Alarm Mask Bits
ALARM 1 REGISTER MASK BITS (BIT 7)
DY/
DT
A1M4
A1M3
A1M2
A1M1
ALARM RATE
X
1
Alarm once per second
X
1
0
Alarm when seconds match
X
1
0
Alarm when minutes and seconds match
X
1
0
Alarm when hours, minutes, and seconds match
0
Alarm when date, hours, minutes, and seconds match
1
0
Alarm when day, hours, minutes, and seconds match
ALARM 2 REGISTER MASK BITS (BIT 7)
DY/
DT
A2M4
A2M3
A2M2
ALARM RATE
X
1
Alarm once per minute (00 seconds of every minute)
X
1
0
Alarm when minutes match
X
1
0
Alarm when hours and minutes match
0
Alarm when date, hours, and minutes match
1
0
Alarm when day, hours, and minutes match
鐩搁棞(gu膩n)PDF璩囨枡
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鍙冩暩(sh霉)鎻忚堪
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